r8a66120ffa Renesas Electronics Corporation., r8a66120ffa Datasheet - Page 10

• Manufacturer Part Number: r8a66120ffa
• Description: 4m-bit X 2 Multiple Field Memory
• Manufacturer: Renesas Electronics Corporation.

Caution When Write Cycle and Read Cycle Approach Each Other
The interval m between write cycle and a read cycle should be secured more than 256 cycles when the write cycle
goes ahead of the read cycle on the following conditions, that is to say the interval less than 255 cycles is forbidden.
When once this restriction to the interval isn’t fulfilled, writing data is guaranteed, but reading data isn't guaranteed
not only for the cycles when it isn’t fulfilled but also for the following 256 cycles after it is fulfilled again.
In this 256 cycles, read disable and read reset cycles are not counted.
But the following condition is an exception to the restriction to forbid the intervals less than 255 cycles.
Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the interval m between
write and read cycles should be secured more than 256 cycles taking account that they are cyclic and serial lines.
Caution of The State of Clock Stopping
Stopping of clock signal of this IC is forbidden during operating of it. "Stopping of clock signal" mean that
CK is fixed at "L" or "H" for more than tck(Max)(=200ns).
When this restriction to tck isn’t fulfilled, all writing data before stopping of clock signal isn't defined.
Once the clock signal stopped, 1 cycle or more of both write reset cycles and read reset cycles should be secured to operate again.
REJ03F0161-0170 Rev.1.70 May.16.2008
R8A66120FFA
page 10 of 14
• Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles (WE or RE ="H").
In the case of read cycle goes ahead of the write cycle or write cycle and read cycle are accorded. It’s exceptions
of the restriction on forbid the intervals less than 255 cycles.
WRES
RRES
WRES, RRES="H"; WE, RE="L", and
• Both write side and read side are activated continuously.
CK
WE
CK
RE
Q
D
n+256
cycle
n cycle
256
t
CK
(n+256)
(n)
n+257
cycle
n+1 cycle
256
(n+257)
(n+1)
n+2 cycle
255
Disable cycle
The data are
defined because it’s
on write disable cycles
the state of clock
stopping
(n+2)
≧t
CK
n+3 cycle
254
(Max)
(n+3)
m≦255、
WRES,RRES=H、WE,RE=L
n+4 cycle
n+258
cycle
254
The data on
forbidden cycles
are not guaranteed
(n+258)
invalid
n+5 cycle
n+259
cycle
254
(n+259)
1 cycle or more of both write reset
cycles and read reset cycles are
needed for continuation.
n+260
cycle
255
Disable cycle
(n+260)
HIGH-Z
n+261
cycle
256
(n+261)
n+6 cycle
n+262
cycle
256
The data of 256 cycles
after the forbidden cycles
are not guaranteed
(n+262)
invalid
n+263
cycle
n+7 cycle
256
(n+263)
･･･
・・・Read side
･･･Write side
"m", the interval
between a write cycle
and a read cycle