pt6105 China Resources Powtech (Shanghai) Co., Ltd, pt6105 Datasheet - Page 9

• Manufacturer Part Number: pt6105
• Description: Multi-cell Battery Management Front End With I 2 C Interface
• Manufacturer: China Resources Powtech (Shanghai) Co., Ltd

Note: Neither the PT6105 nor MCU can write to the status register. It can only be set by abnormal operating
conditions, and, of course, can be automatically reset when the abnormal conditions doesn’t exist (One except is
WDOG which is only reset by MUC).
Table 4. Cell Balancing Control Register (ADDR:02H)
Note: The Cell Balancing Control Register is blocked during discharge.
Table 3. Operating Status Register (ADDR:01H)
China Resources Powtech (Shanghai) Limited
PT6105_DS Rev EN_1.1
BIT 7,6,5,4,3,2,1: The bits control the cell balance on or off.
BIT 0: Reserved for future expansion.
BIT 7,6,5: Reserved for future expansion.
BIT 4: This bit indicates an VIN under voltage condition.
BIT 3: This bit indicates an ADC fail condition.
BIT 2: This bit indicates a load fail condition.
BIT 1: This bit indicates an chip thermal shut down condition.
BIT 0: This bit indicates a discharge short circuit condition.
ADDR REGISTER
0 = Off; (Default)
1 = On.
ADDR
01H
02H
0 = VIN is greater than the UVLO threashold; (Default)
1 = VIN is below the UVLO threashold.
This bit is reset if the UVLO condition is cleared.
0 = ADC works well; (Default)
1 = ADC fail.
This bit is reset if ADC fail condition is cleared or this bit is read.
0 = Load is disconnected under discharge short circuit condition; (Default)
1 = Load is still connected under discharge short circuit condition.
This bit is reset if the load fail condition is cleared or this bit is read.
0 = Chip temperture is less than the thermal shut down threshold; (Default)
1 = Chip temperture is greater than or equal to the thermal shut down threshold.
This bit is reset if the TSD condition is cleared.
0 = Discharge current is less than the short circuit threshold; (Default)
1 = Discharge current is greater than or equal to the short circuit threshold.
This bit is reset after this bit is read.
Operating Status
REGISTER READ/WRITE
Cell Balance READ/WRITE
READ/WRITE
READ
CB7ON
7
Reserved Reserved Reserved
7
CB6ON
6
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6
CB5ON
5
5
CB4ON
4
Multi-cell Battery Management
Front End with I
UVLO
4
CB3ON
3
ADCFAIL
3
CB2ON
2
LDFAIL
2
CB1ON
PT6105
1
2
C Interface
TSD
1
Reserved
0
DSC
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