vp101-5bahp Zarlink Semiconductor, vp101-5bahp Datasheet - Page 6

• Manufacturer Part Number: vp101-5bahp
• Description: 30/50mhz 8-bit Cmos Video Dac
• Manufacturer: Zarlink Semiconductor

Pin name
IOR,IOG,
ADJUST
BLANK
CLOCK
WHITE
COMP
AGND
SYNC
G
R
B
I
V
REF
SYNC
IOB
V
FS
0
0
0
REF
AA
-R
-G
-B
7
7
7
Composite blank control input. A logic ‘0’ forces the IOR, IOG and IOB outputs to the blanking level, as
illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logic zero, the R
G
Composite sync control input. A logic ‘0’ on this input switches off a 40 IRE current source on the I
output. SYNC does not override any other control or data input as shown in Table 1; therefore it should be
asserted only during the blanking interval. It is latched to the rising edge of CLOCK.
Reference white level control input. A logic ‘1’ on this input forces the IOR, IOG and IOB outputs to the white
level, regardless of the R
Red, Green, and Blue data inputs. R
rising edge of CLOCK. Coding is binary. Unused inputs should be connected to either the regular PCB power
or ground plane.
Clock input. The rising edge of CLOCK latches the R
inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be
driven by a dedicated CMOS buffer.
Red, Green, and Blue current outputs. these high impedance current sources are capable of directly driving a
doubly terminated 75 co-axial cable. All outputs, whether used or not, should have the same output load
(Note: A DC path to ground must be maintained).
Sync current output. Typically this current output is directly wired to the IOG output, and enables sync
information to be encoded onto the green channel. A logic ‘0’ on the SYNC input results in no current being
output to this pin, while logic ‘1’ results in the following current being output:
If sync information is not required on the green channel, this output may be connected to V
input tied high, causing the I
Full scale adjust control. A resistor (R
the full video signal (Fig. 3). The current flowing in the R
relationships in Fig. 3 are maintained, regardless of the full scale output current.
The relationship between R
The full scale output current on IOR, IOB (mA) for a given R
Compensation pin. This pin provides compensation for the internal loop amplifier. A 0.01 F ceramic capacitor must
be connected between this pin and the nearest V
Connecting the capacitor to V
rejection.
Voltage reference output. The output from an internal reference circuit, providing 1.2V (typical) reference.A
0.1 F ceramic capacitor must be used to decouple this output to V
Analog ground. All AGND pins must be connected.
Analog power. All V
7
, B
0
-B
7
, and REF WHITE inputs are ignored.
AA
pins must be connected.
0
-R
SET
7
SYNC
, G
AA
IOR, IOB (mA) = 8624 X
and full scale current on IOG (assuming I
0
-G
I
IOG (mA) = 12082 X
rather than to the AGND provides the highest possible power supply noise
SYNC
current source to be turned off, reducing the power consumption.
7
0
and B
, G
SET
(mA) = 3468 X
0
, and B
) connected between this pin and AGND controls the magnitude of
0
-B
7
AA
inputs. It is latched on the rising edge of CLOCK. See table 1.
Description
0
pin.
are the least significant data bits. They are latched on the
0
-R
V
V
R
R
REF
REF
7
SET
SET
V
R
, G
SET
REF
SET
SET
(V)
(V)
( )
0
( )
-G
resistor is equal to 32 LSBs. note that the IRE
(V)
( )
7
is defined as:
and B
387 LSBs
111 LSBs
AA
276 LSBs
.
0
-B
SYNC
7
SYNC, BLANK, and REFWHITE
is connected to IOG) is:
AA
and the SYNC
0
-R
VP101
7
SYNC
, G
0
-
5