rsc-4128 ETC-unknow, rsc-4128 Datasheet - Page 36

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rsc-4128

Manufacturer Part Number
rsc-4128
Description
Speech Recognition Processor
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RSC-4128
Manufacturer:
SENSORY
Quantity:
20 000
RSC-4128
ROTATE Group Instructions
Rotate group instructions apply only directly to register space SRAM locations. The carry flag is affected by these
instructions, but the sign and zero flags are unaffected.
BRANCH Group Instructions
The branch instructions use direct address values rather than offsets to define the target address of the branch.
This implies that binary code containing branches is not relocatable. However, object code produced by the RSC-
4128 assembler contains address references that are resolved at link time, so .OBJ modules are relocatable. The
indirect jump instruction uses an 8-bit operand (“@dest”) to designate an SRAM register pointer to the 16-bit target
address. The “dest” pointer register must be at an even address. The LOW byte of the target address is contained
at the pointer address, and the HIGH byte of the target address is contained at the pointer address+1.
ARITHMETIC/LOGICAL Group Instructions
Arithmetic and logical group instructions apply only to Register Space SRAM locations. The results of the
instruction are always written directly to the SRAM “dest” register. The exceptions are TM and CP instructions,
which do not write the result to the “dest” register and only update the flags register based on the operation’s
outcome. All but the INCrement and DECrement instructions have both register source and immediate source
forms.
In each of the following instructions the sign and zero flags are updated based on the result of the operation. The
carry flag is updated by the arithmetic operations (ADD, ADC, SUB, SUBC, CP, INC, DEC) but it is not affected by
the logical operations (AND, TM, OR, XOR). Note: the carry is set high by SUB, CP, SUBC and DEC when a
borrow is generated.
36
Instruction Opcode Operand 1 Operand 2 Description
RL
RR
RLC
RRC
SHL
SHR
SAR
Instruction Opcode Operand 1 Operand 2 Description
JC
JNC
JZ
JNZ
JS
JNS
JMP
CALL
RET
IRET
JMPR
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
28
29
2A
dest
dest
dest
dest
dest
dest
dest
dest low
dest low
dest low
dest low
dest low
dest low
dest low
-
dest low
-
@dest
-
-
-
-
-
-
-
dest high
dest high
dest high
dest high
dest high
dest high
dest high
dest high
-
-
-
P/N 80-0206-R
rotate left, c set from b7
rotate right, c set from b0 2
rotate left through carry
rotate right through carry 2
shift left, c set from b7,
b0=0
shift right, c set from b0,
b7=0
shift right arithmetic, c
set from b0, b7
duplicated
jump on carry = 1
jump on carry = 0
jump on zflag = 1
jump on zflag = 0
jump on sflag = 1
jump on sflag = 0
jump unconditional
direct subroutine call 3
return from call
return from interrupt 1
jump indirect
Bytes Cycles +Cycles/Waitstate
3
3
3
3
3
3
3
2
1
Bytes
2
2
2
2
2
3
3
3
3
3
3
3
3
4
2
2
Cycles +Cycles/Waitstate
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
1
1
2
© 2006 Sensory Inc.
2
2
2
2
2
2
2
Data Sheet

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