msm5416273 Oki Semiconductor, msm5416273 Datasheet - Page 38

• Manufacturer Part Number: msm5416273
• Description: 262,144-word 16-bit Multiport Dram
• Manufacturer: Oki Semiconductor

FEDS5416273-05
¡ Semiconductor
MSM5416273
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = "L"
WE = "L"
Split write transfer consists of loading 256 words by 16 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. This operation is the same as a mask write operation in RAM, so new and
persistent modes can be supported.
A split write transfer can be performed after a delay of t
from the change of state of the QSF
STS
output is satisfied.
A masked write transfer operation must precede split write transfer. The purpose is to switch the
SAM port from output mode to input mode, and to set the initial TAP location prior to split write
transfer operations.
Programmable SAM Stops in Split Transfer Cycle
The MSM5416273 has a boundary split register operation using programmable stops. If a CBRS
cycle has been performed, the split transfer cycle performs the boundary operation.
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a
SAM location at which the access will change from one half of the SAM to the other half (at the
TAP address).
Lower SAM
Upper SAM
TAP1
TAP3
TAP2
0
255
256
511
S.T. (TAP2)
S.T. (TAP3)
Figure 2. Example of Boundary Split Register
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