s4886 Applied Micro Circuits Corporation (AMCC), s4886 Datasheet

s4886

Manufacturer Part Number

s4886

Description

10 Mbps - 4.25 Gbps Continuous Rate Cdr

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.S4886.pdf (2 pages)

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S4886

10 Mbps - 4.25 Gbps Continuous Rate CDR

Features

• 10 Mbps - 4.25 Gbps continuous rate Clock/

• Standards Compliant*: SONET/SDH, GE, FC,

• Optional power down of unused outputs and

• Two 19 MHz - 670 MHz Differential REFCLK

• Integrated frequency counter

• Optional user interface:

• CDR Retimer mode option supports Built-in-

• Optional CDR Retimer mode differential TX

• Maskable Global Alarm pin indicator

Transmitter (TX) Features

• Integrated CSU programmable frequency syn-

• Differential CML serial data/clock outputs

• Data/Clock source impedance 100 W differen-

• Optional CDR Retimer mode output data

• Optional serial data output squelch to all-1’s,

• TX CSU Loss-of-Lock (LOL) status alarm

• Internal CDR Retimer mode TX FIFO to decou-

Continued on next page...

Data Recovery (CDR) or CDR Retimer mode 1:1

operation

ITU-T G.709, SMPTE-292, DV 6000, FDDI,

FICON and ESCON

internal functions

inputs for CDR Retimer mode optional exter-

nal PLL jitter reduction support

• 3.3V I2C® 100 kbps and 400 kbps compati-

• Optional I2C® enabled SPI compatible

• Pin-based direct programming of sixteen

Self-Test (BIST) 2(7, 23, 31)-1 PRBS or 32-bit

user generator/checker pattern

encoding and/or RX decoding

thesizer with programmable prescaler output

with data output amplitude de-emphasis

tial (50 W SE)

polarity inversion

all-0’s, or alternating 1/0’s during alarm con-

ditions

ple clocks with error status and optional auto

initialization

ble serial interface with maskable inter-

rupt and chip select

serial port with shared maskable interrupt

or alternative 4-bit programmable GPIO

port

predefined modes

Description

The S4886 transceiver is a fully integrated CMOS

10 Mbps - 4.25 Gbps continuous rate auto

ranging Clock and Data Recovery (CDR)

device.Its at-rate serial interface features

wideband differential CML I/O with optionally

enabled data and full rate clock outputs. The

CDR’s continuous rate auto ranging capability

coupled with its low power dissipation (500 mW

max) and small 6 x 6 mm

an ideal solution for any rate any protocol jitter

clean-up/clock recovery and 3R (Reshaping,

Regeneration, and Retiming) transponder

applications. On-chip clock synthesis and clock

recovery PLL components are included in the

S4886 allowing the use of a slower external

clock reference. The chip contains a broadband

RF front-end, two programmable synthesizers, a

clock extractor and retimer, and a transmit

section with rate multiplier and high frequency

clock and data drivers. The S4886 can optionally

search, identify, and auto acquire any rate

compatible data stream. The figure below

shows a typical transponder application.

10 Mbps - 4.25 Gbps

NETWORK SIDE

Continuous-Rate

Network Signal

System Block Diagram with the S4886

form factor makes it

O/E

Optional Jitter

Control PLL

S4886

CDR

Overview

The S4886 is designed for major standards

compliance* and, as such, is well suited for use

as the front end in a wide variety of clock/data

recovery and clock synthesis applications

including that for SONET/SDH and Storage Area

Network (SAN) compatible equipment. To

facilitate use diversity, the S4886 CDR features

three types of user interface: Inter-IC (I2C®) bus,

I2C® with Serial Peripheral Interface (SPI) bus or

standalone direct pin programming of sixteen

predefined modes. Of these sixteen operating

modes, fifteen are popular rate/protocol specific

with the last enabling the S4886 auto ranging

feature for unaided data stream acquisition over

the full breadth of its operating range.

The S4886 internal RX Clock Recovery Unit

(CRU) consists of a high gain (5 mVpp typ) low

jitter high bandwidth Limiting Amplifier (LA)

with Loss of Signal (LOS) detection capability

and an externally referenced high frequency

(HF) phase-locked loop (PLL). The LA is

provisioned with both optional bandwidth

control to maximize the input signal-to-noise

ratio (SNR) and optional decision threshold

adjustment to achieve the best possible Bit

Error Rate (BER) performance. The CRU includes

an optics module signal detect (SD) input and a

Loss-of-Lock (LOL) status indicator output with

programmable error input from such sources as

its integral configurable run length detector.

E/O

PRODUC T BRIEF

10 Mbps - 4.25 Gbps

Continuous-Rate

CLIENT SIDE

Client Signal

Related parts for s4886

s4886 Summary of contents

Page 1

... Of these sixteen operating modes, fifteen are popular rate/protocol specific with the last enabling the S4886 auto ranging feature for unaided data stream acquisition over the full breadth of its operating range. The S4886 internal RX Clock Recovery Unit ...

Page 2

... Low jitter CML differential or single-ended combination of off-frequency, harmonic band, (SE) driven serial high speed high sensitivity RX input: and transition density detection the S4886 will • Internal 100 W differential termination with auto acquire any bit rate within the 10 Mbps - input bias for AC coupling support 4.25 Gbps band and make available acquired • ...

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