w27e040 Winbond Electronics Corp America, w27e040 Datasheet - Page 2

• Manufacturer Part Number: w27e040
• Description: 512k X 8 Electrically Erasable Eprom
• Manufacturer: Winbond Electronics Corp America

FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E040 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to
the output pins. When addresses are stable, the address access time (T
from CE to output (T
T
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E040 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
but higher than GND), OE = V
other address pins equal V
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
V
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
(12V), V
pins equal the desired inputs.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
target chips is inhibited, so that except for the CE and V
common inputs.
OE = V
ACC
IL
.
and T
IL
CC
and V
= V
CE
timings are met.
CP
CC
(5V), CE = V
= V
IH
CE
CP
, V
), and data are available at the outputs T
(5V).
PP
IL
and data input pins equal V
= V
IH
PP
IL,
PP
(2V or above but lower than V
OE = V
is raised to V
/V
PE
(12V/14V), and V
IH
, the address pins equal the desired address, and the input
PE
- 2 -
(14V), V
IH
.
CC
CC
PP
= 5V, erasing or programming of non-
= V
CC
, and V
PP
), A9 = V
CE
OE
= V
(5V), CE = V
after the falling edge of OE, if
PE
CC
(14V), CE = V
, the W27E040 may have
ACC
HH
PP
= V
(14V), A0 = V
) is equal to the delay
PP
PP
IL
W27E040
(12V), CE = V
is raised to V
, (0.8V or below
IH
, and OE =
IL
, and all
IH
PP
,