mt58l512y36d Micron Semiconductor Products, mt58l512y36d Datasheet - Page 8

• Manufacturer Part Number: mt58l512y36d
• Description: 16mb 1 Meg X 18, 512k X 32/36 Pipelined, Dcd Syncburst Sram
• Manufacturer: Micron Semiconductor Products

FBGA PIN DESCRIPTIONS
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
3R, 4P, 4R, 6N, 3R, 4P, 4R, 6N,
10R, 11A, 11P, 10P, 10R, 11P,
8P, 8R, 9P, 9R,
10A, 10B, 10P, 9R, 10A, 10B,
2A, 2B, 3P,
x18
11H
11R
4A
7A
3A
6A
6R
6P
5B
7B
6B
3B
8B
–
–
2A, 2B, 3P,
8P, 8R, 9P,
x32/x36
11H
11R
6R
5B
5A
4A
4B
7A
7B
6B
3A
6A
3B
8B
6P
SYMBOL
OE#(G#)
BWa#
BWb#
BWd#
BWE#
BWc#
GW#
CE2#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
Input
Input
Input
Input
Input
Input
Input
TYPE
Input
Input
Input
(continued on next page)
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb#
controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQd’s and DQPd. Parity is only available on the x18 and
x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
PIPELINED, DCD SYNCBURST SRAM
8
16Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2000, Micron Technology, Inc.
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