mt58l64v32f Micron Semiconductor Products, mt58l64v32f Datasheet
mt58l64v32f
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mt58l64v32f Summary of contents
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... Part Number Example: MT58L64L36FT-8.5 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ MT58L128L18F, MT58L64L32F, MT58L64L36F; MT58L128V18F, MT58L64V32F, MT58L64V36F 3. **JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION MARKING The Micron high-speed, low-power CMOS designs that are fabri- cated using an advanced CMOS process ...
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... GW# CE# CE2 CE2# OE# NOTE: Functional Block Diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...
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... NC DQd 50 *Pin 50 is reserved for address expansion. **No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM (www.micronsemi.com/datasheets/syncds.html) for the latest data sheet. ...
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... SA 100 *Pin 50 is reserved for address expansion. **No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...
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... ADV ADSP# 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...
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... DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b” Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins. ...
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... WRITE Byte “a” WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM THIRD ADDRESS (INTERNAL) X ...
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... ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM ...
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... DC values. AC I/O curves are available upon request should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ...
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... Typical values are measured at 3.3V, 25°C, and 15ns cycle time. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM = +3 ...
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... TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: 1. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM CONDITIONS SYMBOL T = 25° MHz ...
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... This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. 4. This parameter is sampled. 5. Transition is measured ±500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters “Don’t Care” when a byte write enable is sampled LOW. ...
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... The Micron 128K x 18, 64K x 32, and 64K x 36 SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM 2.5V I/O AC TEST CONDITIONS = (V /2 ...
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... I SUPPLY I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, I ...
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... CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled t KQHZ after deselect. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM READ TIMING t ADSS ...
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... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version; or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 ...
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... CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM READ/WRITE TIMING ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and SyncBurst are registered trademarks of Micron Technology, Inc. Pentium is a registered trademark of Intel Corporation. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 FLOW-THROUGH SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) +0 ...
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... Added Note - “Preliminary Package Data” to FBGA Capacitance and Thermal Resistance Tables Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 6/01 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 19 Micron Technology, Inc ...
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... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version; or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 8/00 ...
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... CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 8/00 FLOW-THROUGH SYNCBURST SRAM READ/WRITE TIMING ...
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... NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 8/00 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 165-PIN FBGA 0 ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and SyncBurst are registered trademarks of Micron Technology, Inc. Pentium is a registered trademark of Intel Corporation. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 8/00 FLOW-THROUGH SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) +0 ...
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... Added Note - “Preliminary Package Data” to FBGA Capacitance and Thermal Resistance Tables Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_2.p65 – Rev. 8/00 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 24 Micron Technology, Inc ...