k6r1004v1d Samsung Semiconductor, Inc., k6r1004v1d Datasheet
k6r1004v1d
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k6r1004v1d Summary of contents
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... K6R1004V1D Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Rev. 0.0 Initial document. Rev. 0.1 Speed bin modify Rev. 0.2 Current modify Rev. 1.0 1. Final datasheet release 2. Delete 12ns speed bin. 3. Change Icc for Industrial mode. ...
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... K6R1004V1D 1Mb Async. Fast SRAM Ordering Information Org. Part Number K6R1004C1D-J(K)C(I) 10 256K x4 K6R1004V1D-J(K)C(I) 08/10 K6R1008C1D-J(K,T,U)C(I) 10 128K x8 K6R1008V1D-J(K,T,U)C(I) 08/10 K6R1016C1D-J(K,T,U,E)C(I) 10 64K x16 K6R1016V1D-J(K,T,U,E)C(I) 08/10 VDD(V) Speed ( ns ) PKG 32-SOJ K: 32-SOJ(LF) 3.3 8/ 32-SOJ K : 32-SOJ(LF 32-TSOP2 3.3 8/ 32-TSOP2(LF 44-SOJ K : 44-SOJ(LF 44-TSOP2 3.3 8/ 44-TSOP2(LF 48-TBGA - 2 - PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Temp. & ...
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... GENERAL DESCRIPTION The K6R1004V1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004V1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′ ...
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... K6R1004V1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Value 3ns 1.5V See below , & t WHZ OW OLZ OHZ +3.3V 319Ω D OUT 353 Ω 5pF* K6R1004V1D-10 Unit Min Max ...
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... PU 50 PRELIMINARY PRELIMINARY for AT&T CMOS SRAM K6R1004V1D-10 Unit Max - ...
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... K6R1004V1D NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced ...
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... K6R1004V1D TIMING WAVEFORM OF WRITE CYCLE(3) Address ...
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... K6R1004V1D PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 ±0.12 0.440 ±0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Units:millimeters/Inches 9.40 ±0.25 0.370 ±0.010 +0.10 0.20 -0.05 +0.004 0.008 -0.002 0.69 MIN 0.027 ) 0 ...