gvt71256g18 ETC-unknow, gvt71256g18 Datasheet - Page 3

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gvt71256g18

Manufacturer Part Number
gvt71256g18
Description
256k Synchronous Burst Sram
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
gvt71256g18T
Manufacturer:
FAIRCHILD
Quantity:
10
Part Number:
gvt71256g18T-5
Manufacturer:
GALVANTECH
Quantity:
20 000
PIN DESCRIPTIONS
February 10, 1998
Rev. 2/98
GALVANTECH
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
80, 48, 47, 46, 45, 44, 49, 50
QFP PINS
93, 94
87
88
89
98
92
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ11
DQ12
DQP2
DQ10
DQ13
DQ14
DQ15
DQ16
DQ9
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SYMBO
A0-A17
WEL#,
WEH#
BWE#
CE2#
GW#
CLK
CE#
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
, INC.
100 99
31
32
PIN ASSIGNMENT (Top View)
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
98
33
TYPE
97
34
Input-
Input-
Input-
Input-
Input-
Input-
Input-
96
35
95
36
94
37
100-pin PQFP
100-pin TQFP
256K X 18 SYNCHRONOUS BURST SRAM
93
38
Addresses: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and
HIGH for a READ cycle. WEL# controls DQ1-DQ8 and DQP1. WEH#
controls DQ9-DQ16 and DQP2. Data I/O are high impedance if either of
these inputs are LOW, conditioned by BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and must
meet the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE to occur
independent of the BWE# and WEn# lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write control
and burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to gate
ADSP#.
Chip Enable: This active LOW input is used to enable the device.
92
39
91
40
or
3
90
41
89
42
88
43
87
44
86
45
85
46
84
47
83
48
82
49
81
50
DESCRIPTION
Galvantech, Inc. reserves the right to change products or specifications without notice.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
NC
NC
VCCQ
VSSQ
NC
DQP1
VCCQ
VSS
NC
VCC
ZZ
DQ4
DQ3
DQ1
VSSQ
VCCQ
NC
DQ8
DQ7
VSSQ
DQ6
DQ5
VCCQ
VSSQ
DQ2
NC
NC
NC
NC
GVT71256G18

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