tmpr28051 ETC-unknow, tmpr28051 Datasheet
tmpr28051
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tmpr28051 Summary of contents
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... EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback path is selected (the loopback signal is overwritten by TU-AIS). TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device ...
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Device Advisory for Version 5 of the Device Error Insertion (EI) (continued) EI-3. False S-BIP, L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions ...
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... The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS). TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device Error Insertion (EI) (continued) EI-3. False S-BIP, L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. ...
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... The digital jitter attenuator buffers are not functional. The DJACTL bit in register 0x01 should be set this device. Putting the device in the jitter attenuator mode (DJACTL = 1) causes loss of transmission. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device Actual ...
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Device Advisory for Version 2 of the Device STS Path Overhead (POH) POH-1. False H4LOMF Indication Forcing a SONET/SDH line level decrement (H1, H2) from a value of either 348 or 347 results in false H4LOMF indications. Loss of Data ...
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... The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS). TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device Error Insertion (EI) (continued) EI-3. False S-BIP, L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. ...
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... The test pattern detector always inverts the clock coming into the block before retiming the data. Device Version (DV) DV-1. Device Version Report The device version register, 0x16, reports the device version as 0x02. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device Actual 0.25 2.5 ...
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Device Advisory for Version 3 of the Device AY99-027SONT-2 Replaces AY99-027SONT to Incorporate the Following Updates Added issues RA-5 and EI-3 to the document. For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com ...
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... The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS). TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device Error Insertion (EI) (continued) EI-3. False S-BIP, L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. ...
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... Device Version (DV) DV-1. Device Version Report The device version register, 0x16, reports the device version as 0x03. AY99-028SONT-2 Replaces AY99-028SONT to Incorporate the Following Updates Added issues RA-5 and E1-3 to the document. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device Actual 0.25 2.5 25 ...
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Device Advisory for Version 4 of the Device For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, ...
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... DS1/E1 broadcast SONET/SDH test equipment Description The Lucent Technologies Microelectronics Group TMPR28051 device is designed to map any valid combination of DS1 and E1 signals into a stream at a rate of 51.84 Mbits/s. This device provides all of the functions necessary to insert and drop any valid com- bination asynchronous DS1 signals or 21 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Contents Features ................................................................................................................................................................... 1 Applications .............................................................................................................................................................. 1 Description ................................................................................................................................................................ 1 Block Diagram ..........................................................................................................................................................5 Pin Information ......................................................................................................................................................... 6 Nomenclature Assumptions ....................................................................................................................................10 DS1/E1 to STS-1 Block Descriptions .....................................................................................................................10 LOC and AIS Monitor .........................................................................................................................................10 DS1/E1 Loopback Select Logic ..........................................................................................................................10 Input Select Logic ...............................................................................................................................................10 Elastic Store .......................................................................................................................................................11 VT Generate .......................................................................................................................................................11 STS-1/AU-3 Generate ........................................................................................................................................13 SPE Insertion Logic ............................................................................................................................................14 STS-1 to DS1/E1 Block Descriptions .....................................................................................................................16 Loopback Select Logic ...
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... Figure 15. Bus Parallel Mode Receive Sync Timing ..............................................................................................71 Figure 16. SDH/SONET Path Termination Multiplex Application ...........................................................................72 Figure 17. Digital Cross Connect Application .........................................................................................................72 Figure 18. Test Pattern Usage for Complete System ............................................................................................73 Figure 19. Test Pattern Usage for End-to-End Operation ......................................................................................73 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper List of Figures Page 3 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Tables Table 1. Pin Descriptions ......................................................................................................................................... 7 Table 2. VT1.5 Overhead Byte Format (V5) .......................................................................................................... 11 Table 3. RFI-V, RDI-V Description ........................................................................................................................ 11 Table 4. VT1.5 Superframe ................................................................................................................................... 12 Table 5. VT2 Superframe ...................................................................................................................................... 12 Table 6. STS-1 Overhead Byte Allocation ............................................................................................................. 13 Table 7. G1 Path Condition/Performance Byte Format ......................................................................................... 13 Table 8. VT1.5 SPE Insertion Format .................................................................................................................... 15 Table 9. Mapping of VT1 (VT Group #, VT #) .............................................................................................. 15 Table 10 ...
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... PLL-free operation. The TMPR28051 device contains built-in test pattern insertion and drop that allows end-to-end testing for initial setup or maintenance without the need for external test equipment. Built-in loopbacks at both the STS-1 and DS1/ E1 sides provide maximum flexibility for use in a number of SONET/SDH or DS1/E1 products including terminal multiplexers, add/drop multiplexers, and digital cross connects ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Pin Information VSS 1 VSS 2 TCLK10 3 TDATA10 4 RCLK10 5 RDATA10 6 RDATA9 7 RCLK9 8 TDATA9 9 TCLK9 10 TCLK8 11 VDD 12 TDATA8 13 RCLK8 14 RDATA8 15 RDATA7 16 RCLK7 17 TDATA7 18 TCLK7 19 TCLK6 20 VSS 21 TDATA6 22 RCLK6 23 RDATA6 24 RDATA5 25 VDD 26 RCLK5 27 TDATA5 28 TCLK5 29 TCLK4 30 VSS 31 TDATA4 32 RCLK4 33 RDATA4 34 RDATA3 ...
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... I indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will tolerate their inputs. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Type* Name/Description O Transmit DS1/E1 Clock. DS1/E1 clock output. E1 signals can only occupy TCLK[1:21] ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol Type* 179 MPMUX I 180 MPMODE I 181 RD_R/W I 178 ALE_AS INT O 183 RDY_DTACK O 48—50, AD[7:0] I/O 55—59 60—64, A[7:0] I 66—68 176 WR_DS I 106 RESET u I 184 TCK ...
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... I indicates an internal pull-up; I indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will tolerate their inputs. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Type* Name/Description u Boundary-Scan Input Data. This pin has an internal resistor ...
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... DS1 or E1, respec- tively. This allows users of the Lucent Technologies T7698FL3/T7693 devices to reuse the XCLK on the board. The TMPR28051 is provisioned to accept the exact DS1 rate by default (BLUECLKSEL = 0 in bit 2 of register 0x00), but can be changed to perform the divide-by-16 function (BLUECLKSEL = 1 in bit 2 of reg- ister 0x00) ...
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... This corre- sponds to 0x6869 for the V1 and V2 bytes within the VT2 superframe. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper In this block, the DS1/E1 data is placed into the VT, and the VT overhead is generated. The format of the VT overhead byte, V5, is shown in Table 2. ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper DS1/E1 to STS-1 Block Descriptions (continued) VT Generate (continued) In addition to generating the superframe, this block automatically generates the BIP-2 signal. Each VT can be configured to intentionally insert continuous BIP-2 errors for troubleshooting purposes (BIP2ERINS[1:28 bit 7 of registers 0x4F—0x6A). This BIP error insert field forces errors on both BIP-2 bits ...
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... DS1_E1N (bit 0 in register 0x07) is high, or all 1s when DS1_E1N is low. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper The device inserts the correct frame pattern of 0xF628 into the A1 and A2 bytes. The device inserts a fixed value of 0x01 into the J0 byte ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper DS1/E1 to STS-1 Block Descriptions (continued) STS-1/AU-3 Generate (continued) Path remote error indicator (REI-P) reports the number of remote errors. The four REI-P bits contain the num- ber of B3 BIP-8 errors detected in the current frame when REI_EN = 1 (bit 7 of register 0x01). Valid values for these 4 bits are 0000— ...
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... VT2 # (VT Group #, VT #) VT2 # Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued • • • • • • V ...
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... There are two parallel modes of operation: bus mode and nonbus mode. Bus mode allows multiple TMPR28051 devices to operate on a 19.44 MHz bus; in nonbus mode, the device transmits data in a point-to-point fashion at 6.48 MHz. In either parallel mode, the device sends a parity bit with the data ...
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... OOF. The running and latched counts for B3 counters are held at zero during OOF as well as LOP-P. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper The device can be provisioned to count bits in error (BIPBLKCNT = 0 in bit 1 of register 0x00) or blocks in error (BIPBLKCNT = 1 in bit 0 of register 0x00). ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper STS-1 to DS1/E1 Block Descriptions (continued) VT Terminate (continued) AIS-V is declared on three consecutive superframes with all 1s in the V1 and V2 bytes. AIS-V and LOP-V are mutually exclusive conditions. If neither VTAIS[1:28] (bit 3 in registers 0x6B—0x86) or VTLOP[1:28] (bit 6 in registers 0x6B—0x86 logic 1, then the pointer interpreter declares a normal pointer ...
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... O.151 compliant, so they can be used to drive external test equipment as well as to perform internal maintenance and troubleshooting. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Test Pattern Drop The test pattern detector can detect the same four test sequences generated by the test pattern generator (RCV_PAT-[1:0] in bit positions 4 and 5 of register 0x08) ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Overview The device is equipped with an asynchronous microprocessor interface that allows operation with most commer- cially available microprocessors. Inputs MPMUX and MPMODE are used to configure this interface into one of four possible modes. The MPMUX setting selects either a multiplexed 8-bit address/data bus (AD[7:0]), or a demulti- plexed 8-bit address bus (A[7:0]) and an 8-bit data bus (AD[7:0]) ...
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... Configuration Device Pin Name Mode 1 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0] A[7:0] Mode 2 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Generic Pin Pin Type Assertion Name Sense DS Input Active-Low R/W Input AS Input CS Input Active-Low INT Output Active-High DTACK ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Microprocessor Interface Pins Table 13. Mode [1—4] Microprocessor Pin Definitions (continued) Configuration Device Pin Name Mode 3 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0] A[7:0] Mode 4 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0] 22 (continued) (continued) Generic Pin Pin Assertion Name Type ...
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... S1#DET-3 S1#DET-2 15 00010101 DEVID-7 DEVID-6 16 00010110 0 0 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 Control, Alarm, and Mask Bit Registers B2ERRINS B3ERRINS LATCH_CNT BLUECLKSEL TXPAISINS DJACTL 0 RXPARITY TXPARITY RXSTS1EDGE TXSTS1EDGE RXDS1EDGE 0 H4LOMF ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 17 00010111 DS1/E1AIS1 DS1/E1LOC1 18 00011000 DS1/E1AIS2 DS1/E1LOC2 19 00011001 DS1/E1AIS3 DS1/E1LOC3 1A 00011010 DS1/E1AIS4 DS1/E1LOC4 1B 00011011 DS1/E1AIS5 DS1/E1LOC5 1C 00011100 DS1/E1AIS6 DS1/E1LOC6 1D 00011101 DS1/E1AIS7 DS1/E1LOC7 ...
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... RXESOF23 4A 01001010 0 RXESOF24 4B 01001011 0 RXESOF25 4C 01001100 0 RXESOF26 4D 01001101 0 RXESOF27 4E 01001110 0 RXESOF28 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 VT Drop Selection Registers TXESOF1 VTDROP4_1 VTDROP3_1 TXESOF2 VTDROP4_2 VTDROP3_2 TXESOF3 VTDROP4_3 VTDROP3_3 TXESOF4 VTDROP4_4 VTDROP3_4 TXESOF5 VTDROP4_5 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 4F 01001111 BIP2ERINS1 VTRFIRDIEN1 VTRFIINS1 50 01010000 BIP2ERINS2 VTRFIRDIEN2 VTRFIINS2 51 01010001 BIP2ERINS3 VTRFIRDIEN3 VTRFIINS3 52 01010010 BIP2ERINS4 VTRFIRDIEN4 VTRFIINS4 53 01010011 BIP2ERINS5 VTRFIRDIEN5 VTRFIINS5 54 01010100 BIP2ERINS6 ...
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... DJASCALE-6 DJASCALE-5 DJASCALE-4 DJASCALE-3 DJASCALE-2 DJASCALE-1 DJASCALE-0 8D 10001101 DJAGTHR-23 DJAGTHR-22 DJAGTHR-21 DJAGTHR-20 DJAGTHR-19 DJAGTHR-18 DJAGTHR-17 DJAGTHR-16 8E 10001110 DJAGTHR-15 DJAGTHR-14 DJAGTHR-13 DJAGTHR-12 DJAGTHR-11 DJAGTHR-10 DJAGTHR-9 8F 10001111 DJAGTHR-7 DJAGTHR-6 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit Drop Monitoring Registers VTRDI1_1 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 90 10010000 0 0 STS-1 LOS Detect/Test Pattern Edge Control Register 91 10010001 LOSDET-7 LOSDET-6 92 10010010 RESERVED RESERVED 93 10010011 RESERVED RESERVED 94 10010100 RESERVED RESERVED ...
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... D5 11010101 BIP2CNT7_8 BIP2CNT6_8 BIP2CNT5_8 BIP2CNT4_8 D6 11010110 VT9PTR+3 VT9PTR+2 D7 11010111 BIP2CNT7_9 BIP2CNT6_9 BIP2CNT5_9 BIP2CNT4_9 D8 11011000 VT10PTR+3 VT10PTR+2 D9 11011001 BIP2CNT7_10 BIP2CNT6_10 BIP2CNT5_10 BIP2CNT4_10 BIP2CNT3_10 BIP2CNT2_10 BIP2CNT1_10 BIP2CNT0_10 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 Reserved Registers (continued) RESERVED RESERVED RESERVED ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 Block Registers 0xC0—0xFF: Detected BIP Errors (continued) DA 11011010 VT11PTR+3 VT11PTR+2 DB 11011011 BIP2CNT7_11 BIP2CNT6_11 BIP2CNT5_11 BIP2CNT4_11 BIP2CNT3_11 BIP2CNT2_11 BIP2CNT1_11 BIP2CNT0_11 DC 11011100 VT12PTR+3 ...
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... VT17PTR–2 E7 11100111 VTREI7_17 VTREI6_17 E8 11101000 VT18PTR–3 VT18PTR–2 E9 11101001 VTREI7_18 VTREI6_18 EA 11101010 VT19PTR–3 VT19PTR–2 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 Block Registers 0xC0—0xFF: Detected REI Errors Register 0xBF Settings: REI_CNTS = 1, BIP_CNTS = ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 Block Registers 0xC0—0xFF: Detected REI Errors (continued) EB 11101011 VTREI7_19 VTREI6_19 EC 11101100 VT20PTR–3 VT20PTR–2 ED 11101101 VTREI7_20 VTREI6_20 EE 11101110 VT21PTR–3 VT21PTR– ...
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... E4 11100100 RJ1BYTE7_28 RJ1BYTE6_28 RJ1BYTE5_28 RJ1BYTE4_28 RJ1BYTE3_28 RJ1BYTE2_28 RJ1BYTE1_28 RJ1BYTE0_28 E5 11100101 RJ1BYTE7_27 RJ1BYTE6_27 RJ1BYTE5_27 RJ1BYTE4_27 RJ1BYTE3_27 RJ1BYTE2_27 RJ1BYTE1_27 RJ1BYTE0_27 E6 11100110 RJ1BYTE7_26 RJ1BYTE6_26 RJ1BYTE5_26 RJ1BYTE4_26 RJ1BYTE3_26 RJ1BYTE2_26 RJ1BYTE1_26 RJ1BYTE0_64 E7 11100111 RJ1BYTE7_25 RJ1BYTE6_25 RJ1BYTE5_25 RJ1BYTE4_25 RJ1BYTE3_25 RJ1BYTE2_25 RJ1BYTE1_25 RJ1BYTE0_25 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 Block Registers 0xC0—0xFF: Receive J1 Path Trace Bytes (continued) E8 11101000 RJ1BYTE7_24 RJ1BYTE6_24 RJ1BYTE5_24 RJ1BYTE4_24 RJ1BYTE3_24 RJ1BYTE2_24 RJ1BYTE1_24 RJ1BYTE0_24 E9 11101001 RJ1BYTE7_23 RJ1BYTE6_23 RJ1BYTE5_23 RJ1BYTE4_23 RJ1BYTE3_23 RJ1BYTE2_23 RJ1BYTE1_23 RJ1BYTE0_23 ...
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... E3 11100011 TJ1BYTE7_29 TJ1BYTE6_29 TJ1BYTE5_29 TJ1BYTE4_29 TJ1BYTE3_29 TJ1BYTE2_29 TJ1BYTE1_29 TJ1BYTE0_29 E4 11100100 TJ1BYTE7_28 TJ1BYTE6_28 TJ1BYTE5_28 TJ1BYTE4_28 TJ1BYTE3_28 TJ1BYTE2_28 TJ1BYTE1_28 TJ1BYTE0_28 E5 11100101 TJ1BYTE7_27 TJ1BYTE6_27 TJ1BYTE5_27 TJ1BYTE4_27 TJ1BYTE3_27 TJ1BYTE2_27 TJ1BYTE1_27 TJ1BYTE0_27 E6 11100110 TJ1BYTE7_26 TJ1BYTE6_26 TJ1BYTE5_26 TJ1BYTE4_26 TJ1BYTE3_26 TJ1BYTE2_26 TJ1BYTE1_26 TJ1BYTE0_26 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Bit 5 Bit 4 Bit 3 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Map (continued) Table 14. Device Register Map (continued) Address Bit 7 Bit 6 Block Registers 0xC0—0xFF: Transmit J1 Path Trace Bytes (continued) E7 11100111 TJ1BYTE7_25 TJ1BYTE6_25 TJ1BYTE5_25 TJ1BYTE4_25 TJ1BYTE3_25 TJ1BYTE2_25 TJ1BYTE1_25 TJ1BYTE0_25 E8 11101000 TJ1BYTE7_24 TJ1BYTE6_24 TJ1BYTE5_24 TJ1BYTE4_24 TJ1BYTE3_24 TJ1BYTE2_24 TJ1BYTE1_24 TJ1BYTE0_24 ...
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... BLUECLKSEL 1 BIPBLKCNT 0 — Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) Function The bits in the register 0x00 are used for device-level con- trol and error reporting. Factory Test Mode. TEST_CNT = 1 forces all internal counters to test mode and is intended for factory use only. ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued) Address Bit # Name (Hex) 0x01 — — 7 REI_EN 6 AUTO_LRDI 5 TXPAISINS 4 DJACTL 3 — 2 STS1SCR 1 STS1DSCR 0 STS1LB 38 (continued) (continued) Function The bits in register 0x01 are used to provision device-level control bits ...
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... TXSTS1EDGE 1 RXDS1EDGE 0 TXDS1EDGE Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x02 are used to set the edges that retime data into and out of the device. Receive Serial Data, Transmit Serial Data. Both the RXSERIAL and TXSERIAL bits are used to set the type of STS-1 data. When either serial bit is written to 1, the STS-1 rail runs in serial mode ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued) Address Bit # Name (Hex) 0x03 — — 7 TRACEER 6 RXPARER 5 — 4 H4LOMF 3 STS1PAIS 2 STS1LOP 1 STS1LOF 0 STS1OOF 0x04 7 TRACEERMSK 6 RXPARERMSK 5 — 4 H4LOMFMSK ...
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... VTLABCOM 1 AISLOCCOM 0 STS1LOS Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x05 are used to report problems at the receive DS1/E1 and VT level. The bits in this register are composite bits. The bits that report the problems at the VT level are located in 28 separate registers (one for each VT) as described below ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued) Address Bit # Name (Hex) 0x06 7 ESOFMSK 6 VTSIZEMSK 5 VTLOPMSK 4 VTRFIRDIMSK 3 VTAISMSK 2 VTLABMSK 1 AISLOCMSK 0 STS1LOSMSK 0x07 7—1 — 0 DS1_E1N 0x08 7 LATCH_TP 6 RCV_FRAME ...
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... F2-[7:0] 0x0C 7—0 C2-[7:0] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x09 are used to set up the test pattern. TP_DS1E1N = 1 sets the frame sequence to DS1; TP_DS1E1N = 0 sets the frame sequence to E1. TP_INVERT = 1 forces the test pattern sequence to be inverted ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued) Address Bit # Name (Hex) 0x0D — — 7 G1-5 6 G1-6 5 G1-7 4 G1-8 3 — 2 K2-6 1 K2-7 0 K2-8 0x0E — — 7 C2#DET-3 6 C2#DET-2 5 C2#DET-1 4 C2#DET-0 3 F2#DET-3 2 F2#DET-2 ...
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... TBUSMODE 1 TBUSPOS-1 0 TBUSPOS-0 Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x11 are used to set the values to be transmitted in the G1 and K2 bytes. The G1INS-[5:8] bits are used to set values to be transmit- ted in the four least significant bits of the G1 byte. The G1 byte is written by the microprocessor ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued) Address Bit # Name (Hex) 0x13 7—4 — 3 S1INS-3 2 S1INS-2 1 S1INS-1 0 S1INS-0 0x14 7 S1#DET-3 6 S1#DET-2 5 S1#DET-1 4 S1#DET-0 3 S1-3 2 S1-2 1 S1-1 0 S1-0 0x15 7—0 ...
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... DS1/E1INS2_[1:21] 1 DS1/E1INS1_[1:21] 0 DS1/E1INS0_[1:21] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) — Registers 0x17—0x2B report DS1 or E1 conditions. The DS1/E1AIS[1:21] bits report the received DS1/E1 AIS condition. When any of these bits is 1, the corre- sponding DS1/E1 input has an AIS condition. This value represents the current received state ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 16. Registers 0x17—0x32: DS1/E1 Insertion Selection (continued) Address Bit # Name (Hex) 0x2C—0x32 — — 7 DS1AIS[22:28] 6 DS1LOC[22:28] 5 DS1LB[22:28] 4 DS1INS4_[22:28] The DS1/E1INS[4:0]_[1:21] and DS1INS[4:0]_[22:28] bits 3 DS1INS3_[22:28] 2 DS1INS2_[22:28] 1 DS1INS1_[22:28] 0 DS1INS0_[22:28] 48 (continued) (continued) Function Registers 0x17— ...
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... RXESOF[1:28] 5 TXESOF[1:28] 4 VTDROP4_[1:28] These bits in registers 0x33—0x4E are used to select the 3 VTDROP3_[1:28] 2 VTDROP2_[1:28] 1 VTDROP1_[1:28] 0 VTDROP0_[1:28] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) 5 Programmed DS1/E1INS[4:0]_x Bits Address Bit 4 Bit 3 Bit • ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Table 19. VT Drop Selection Format VT1.5 Drop # VT Group # • • • • Table 20 Address Mapping VT # Address • • • • ...
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... VTLABINS2_[1:28] The VTLABINS[2:0]_[1:28] bits directly program the 1 VTLABINS1_[1:28] 0 VTLABINS0_[1:28] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) — The bits in these registers provision the transmitted VT overhead byte, V5. Each BIP2ERINS[1:28] bit = 1 forces the selected VT to transmit inverted BIP-2 bits which causes the down- stream receiver to declare continuous BIP-2 errors ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Rx VT Drop Monitoring (0x6B—0x86) Table 22. Registers 0x6B—0x86 Drop Monitoring Address Bit # Name (Hex) 0x6B—0x86 — — 7 VTSIZEER[1:28] The VTSIZEER[1:28] bits report incorrect VT size bits 6 VTLOP[1:28] 5 VTRDI1_[1:28] 4 VTRDI0_[1:28] ...
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... RVTG-2 1 RVTG-1 0 ROVERRIDE Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x88 are used to override the DS1_E1N signal pin. These bits represent the seven VT Groups and can be individually programmed as follows. If TVTG the signal will be DS1; otherwise, the signal will be E1 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Digital Jitter Attenuator Controls (0x8A—0x8F) Table 24. Registers 0x8A—0x8F: Digital Jitter Attenuator Controls Address Bit # Name (Hex) 0x8A—0x8F — — 0x8A 7—0 SCALETHR-[7:0] Scale Threshold. 0x8B 7—0 DJASCALE-[15:8] Scale Value. ...
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... LOSDET-0/ TP_EDGE-0 0x92—0xBE 7—0 — Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function The bits in register 0x91 are used to set the number of 6.48 MHz clock periods required to declare received STS-1 loss of signal. The two least significant bits have a dual pur- pose and can also be used to program the edge on which the QRSS pattern generator and detector data is clocked ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Block Control (0xBF) Table 26. Register 0xBF: Block Control Address Bit # Name (Hex) 0xBF — — 7—4 — 3 TJ1BYTE 2 RJ1BYTE 1 REI_CNTS 0 BIP_CNTS 56 (continued) (continued) Function The bits in register 0xBF control the information presented to the microprocessor from the registers 0xC0— ...
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... SPTR+[7:0] 0xFF 7—0 SPTR–[7:0] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function Registers 0xC0—0xC5. The first six registers in the block, 0xC0—0xC5, are the BIP errors detected by B1, B2, and B3. Registers 0xC6—0xFD. The remaining registers in the block indicate the errors seen by the BIP-2 error detec- tors in the individual VT1 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description Register Architecture Description Detected REI Errors (0xC0—0xFD) Table 29. Registers 0xC0—0xFD: Detected REI Errors Note: Bits in registers 0xC0—0xFF can have one of four configurations, depending upon the setting of register 0xBF. When register 0xBF is set for BIP_CNTS = 0 and REI_CNTS = 1, the bytes in registers 0xC0—0xFD are used to count the number of REI errors detected by the device ...
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... TJ1BYTE2_[64:1] 1 TJ1BYTE1_[64:1] 0 TJ1BYTE0_[64:1] Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) (continued) Function sponds to the first byte in the 64-byte sequence, while the J1 path trace byte RJ1BYTE[7:0]_1 corresponds to the last byte in the 64-byte sequence. These specified receive J1 byte values are continuously written, modulo 64, into the 0xC0— ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description I/O Timing The I/O timing specifications for the microprocessor interface are given in Table 33. The microprocessor interface pins use CMOS I/O levels (see pages 20—22 for pin listings). All outputs, except the address/data bus AD[7:0], are rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write cycle time is 200 ns for all device configurations ...
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... R/W DS DTACK AD[7:0] Figure 3. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = A[7:0] R/W DS DTACK AD[7:0] Figure 4. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) MINIMUM READ CYCLE t11 t2 t1 VALID ADDRESS t4 t3 t12 VALID DATA MINIMUM WRITE CYCLE ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description I/O Timing (continued R/W DS DTACK VALID AD[7:0] DATA ADDRESS Figure 5. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = R/W DS DTACK VALID AD[7:0] DATA Figure 6. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) 62 (continued) MINIMUM READ CYCLE t11 t4 t3 t12 ...
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... RDY Figure 7. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) CS ALE A[7:0] WR AD[7:0] t27 RDY Figure 8. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper (continued) MINIMUM READ CYCLE t32 t19 t20 VALID ADDRESS t21 t33 t22 t24 VALID DATA ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Microprocessor Interface Description I/O Timing (continued) CS ALE RD VALID AD[7:0] DATA t27 RDY Figure 9. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) CS ALE WR VALID AD[7:0] DATA t27 RDY Figure 10. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) 64 (continued) MINIMUM READ CYCLE t32 t21 ...
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... The HBM ESD threshold presented here was obtained by using these circuit parameters. Table 35. ESD Threshold Voltage Model HBM CDM (all pins except corner pins) CDM (all corner pins) Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Symbol Min Max V –0 – ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Operating Conditions Table 36. Recommended Operating Conditions Parameter Power Supply (dc Voltage) Ground Input Voltage, High Input Voltage, Low Ambient Temperature Power Dissipation, DS1 ( ° 3.3 V Full Loopback Broadcast Standby Power Dissipation ° 3.3 V Full Loopback ...
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... Clock Pulse High Time Peak-to-Peak Jitter RSTS1CLK Frequency Clock Pulse High Time Peak-to-Peak Jitter JTAG Signal TCK Frequency Clock Pulse High Time Peak-to-Peak Jitter Rise/Fall Time Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Min Max Unit 51.839 51.841 MHz — ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Timing Characteristics (continued) Operational Timing (continued) Table 39 lists the setup time (t ) and hold time (t SU tal system interface timing is shown in Figure 11. Table 39. Input Timing Specifications Input Name Reference CLK* TSTS1SYNC TSTS1CLKIN RDATA[1:28] RCLK[1:28] RSTS1DATA[7:0] RSTS1CLK RSTS1PAR RSTS1CLK ...
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... TSTS1PAR TSTS1CLKIN TSTS1DATA7 TSTS1CLKIN TDO TCK * Propagation delay skew, t —t is ±200 ps. PLH PHL, Notes: represents a low-to-high transition. represents a high-to-low transition. Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper Rise Time Test t R Conditions Min Max — — ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Timing Characteristics (continued) Transmit Sync Timing In all transmit modes, the first bit/byte of the J0, J1, and V1 bytes are coincident with the sync pulse. The second and third pulses in this composite signal are only needed to force V1 superframe alignment. If there are three sync pulses as shown below, then V1 will be forced ...
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... The bus parallel mode receive sync timing is shown below in Figure 15. RSTS1CLK RSTS1SERIAL RSTS1DATA J0#1 J0#2 J0#3 J1#1 J1#2 Note: The # symbol followed by a number represents the active device on the bus. Figure 15. Bus Parallel Mode Receive Sync Timing Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper J1#3 V1#1 V1#2 V1#3 5-6347(F).b 5-6347(F).cr.1 71 ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Typical Uses Path Termination Multiplex Using the device without internal loopbacks results in an SDH/SONET path terminating multiplex, as shown in Figure 16. T7693 QUAD LIU DS1/ LIU DS1/E1 #1 OUT DS1/ LIU DS1/E1 #n OUT Note: n represents for DS1 or E1, respectively. ...
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... The internal test pattern generator can be used to test connectivity within a link by setting up a test pattern inser- tion at one end and a drop at the other, as shown in Figure 19. TEST PATTERN SOURCE Figure 19. Test Pattern Usage for End-to-End Operation Lucent Technologies Inc. TMPR28051 STS-1/AU-3 (STM-0) Mapper TMPR28051 TMPR28051 MAPPER TEST ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper Outline Diagram 208-Pin SQFP Dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP 1.30 REF 0.25 GAGE PLANE SEATING PLANE DETAIL A 74 30.60 ± 0.20 28.00 ± 0.20 157 104 DETAIL B 0.25 MIN 0.17/0.27 0.50/0.75 Data Sheet August 1999 156 28.00 ± 0.20 30.60 ± 0.20 105 3.40 ± 0.20 4.10 MAX SEATING PLANE 0 ...
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... Page 71, Figure 15, Bus Parallel Mode Receive Sync Timing, corrected pin name. 21. Page 75, updated device code. 22. TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device , TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device , TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device , ...
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... TMPR28051 STS-1/AU-3 (STM-0) Mapper For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel ...