w49v002a Winbond Electronics Corp America, w49v002a Datasheet - Page 7

• Manufacturer Part Number: w49v002a
• Description: 256k X 8 Cmos Flash Memory With Lpc Interface
• Manufacturer: Winbond Electronics Corp America

STANDARD LPC MEMORY CYCLE DEFINITION
Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later.
FIELD
Start
Cycle Type & Dir
TAR
Addr.
Sync.
Data
NO. OF CLOCKS
1
1
2
8
N
2
"0000b" appears on LPC bus to indicate the initial
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
Turned Around Time
Address Phase for Memory Cycle. LPC supports the 32 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and
Address[3:0] on LAD[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4]
on LAD[3:0] last.)
DESCRIPTION
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Preliminary W49V002A
Publication Release Date: April 2001
Revision A1