m28f201-150xn6tr STMicroelectronics, m28f201-150xn6tr Datasheet - Page 7

• Manufacturer Part Number: m28f201-150xn6tr
• Description: 256k Chip Erase Flash Memory
• Manufacturer: STMicroelectronics

Table 9. Read Only Mode AC Characteristics
((T
Note: 1. Sampled only, not 100% tested
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an ad-
dressed byte. Erase Verify Mode is set-up by writ-
ing A0h to the command register and at the same
time supplying the address of the byte to be veri-
fied. The rising edge of W during the set-up of the
first Erase Verify Mode stops the Erase operation.
Symbol
t
t
t
t
GLQX
EHQZ
GHQZ
ELQX
t
t
t
t
t
A
t
WHGL
AVQV
GLQV
AXQX
ELQV
AVAV
= 0 to 70 C, –40 to 85 C or –40 to 125 C)
(1)
(1)
(1)
(1)
t
t
Alt
t
t
t
ACC
t
t
OLZ
t
RC
OE
OH
LZ
CE
DF
Write Enable High to
Output Enable Low
Read Cycle Time
Address Valid to
Output Valid
Chip Enable Low to
Output Transition
Chip Enable Low to
Output Valid
Output Enable Low
to Output Transition
Output Enable Low
to Output Valid
Chip Enable High to
Output Hi-Z
Output Enable High
to Output Hi-Z
Address Transition
to Output Transition
Parameter
Test Condition
E = V
E = V
E = V
G = V
G = V
G = V
E = V
E = V
E = V
IL
IL
IL
, G = V
, G = V
, G = V
IL
IL
IL
IL
IL
IL
IL
IL
IL
Min Max
The following read cycle is made with an internally
generated margin voltage applied; reading FFh
indicates that all bits of the addressedbyte are fully
erased. The whole contents of the memory are
verified by repeating the Erase Verify Operation,
first writing the set-up code A0h with the address
of the byte to be verified and then reading the byte
contents in a second read cycle.
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not FFh, another
Erase operation is performed and verification con-
tinues from the address of the last verified byte. The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
Interface
70
5V 10%
EPROM
6
0
0
0
0
0
V
-70
CC
=
70
70
25
25
25
Min Max
Interface
90
5V 10%
EPROM
6
0
0
0
0
0
V
-90
CC
=
M28F201
90
90
30
30
30
Min Max Min
120
Interface
5V 10%
EPROM
6
0
0
0
0
0
V
-120
CC
120
120
=
35
30
30
150
Interface
5V 10%
EPROM
6
0
0
0
0
0
V
-150
CC
M28F201
Max
150
150
=
40
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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