psb4595 ETC-unknow, psb4595 Datasheet - Page 28

• Manufacturer Part Number: psb4595
• Description: Analog Line Interface Solution Alis
• Manufacturer: ETC-unknow

The data transfer is synchronized by DCLK. DIN is latched at the falling edge of DCLK,
while DOUT changes with the rising edge of DCLK. During the execution of a command
which is followed by output data (read command), the device will not accept any new
command via DIN. The data transfer sequence can be interrupted by setting CS to ’1’.
To reduce the number of connections to the
strapped together to form a bi-directional data pin.
5.2.2
A serial data interface is used for transferring voice data. The interface consists of five
pins:
DAT_CLK:
FSC:
DAT_IN:
DAT_OUT:
The Frame Sync (FSC) pulse identifies the beginning of a receive and a transmit frame.
DAT_CLK synchronizes the data transfer on DAT_IN and DAT_OUT. The data bytes are
first serialized to 16-bit width and MSB. The rising edge indicates the start of the bit, while
the falling edge is used to latch the contents of the received data.
Figure 15 Example of a Clock Rate of 128 kb/s
Semiconductor Group
The Data Interface
FSC
DAT_CLK
DAT_IN
DAT_OUT
Clock, 128 kHz to 1024 kHz
Frame synchronization clock, 8 kHz
Transmit data input
Receive data output
0
0
15
15
14 13 12
14 13 12
11
11
16 Bit Voicedata MSB first
10 9 8
10 9 8
28
125 µS
7
7
-processor, DIN and DOUT may be
6 5 4
6 5 4
Analog Line Interface Solution
3
3
2 1 0
2 1 0
Configuration Overview
PSB 4595 / PSB 4596
1 2
1 2
Data Sheet 06.98