adc-321 C&D Technologies., adc-321 Datasheet

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adc-321

Manufacturer Part Number
adc-321
Description
8-bit, 50mhz Video A/d Converter
Manufacturer
C&D Technologies.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADC-321
Manufacturer:
ADI
Quantity:
215
FEATURES
GENERAL DESCRIPTION
The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub-
ranging A/D converter. The ADC-321 achieves a sampling rate
comparable to flash converters by employing a sub-ranging
technique which uses multiple comparator blocks each
containing a sample-and-hold amplifier. The ADC-321 can
operate with either a single +5V or dual +5V and +3.3V power
source to allow easy interfacing with 3.3V logic.
An optional synchronous clamp function useful for video signal
processing is provided. The ADC-321 is well suited for the
portable video signal processors due to its low 125mW typical
power dissipation. The ADC-321 also features ±0.5 LSB max.
differential non-linearity, a self bias function that can eliminate the
need for external references, SNR with THD of 45dB, a small
32-pin QFP package and an operating temperature range
of –40 to +85°C
DATEL, Inc., Mansfield, MA 02048 (USA.)
Low power dissipation (180mW max.)
Input signal bandwith (100MHz)
Optional synchronized clamp function
Low input capacitance (15pF typ.)
+5V or +5V/+3.3V power supply operation
Differential nonlinearity (±½LSB max.)
Optional self-biased reference
CMOS/TTL compatible inputs
Outputs 3-state TTL compatible
Surface mount package
®
CLAMP CONTROL
CLAMP ENABLE
OBSOLETE PRODUCT
DGND
AGND
AGND
Contact Factory for Replacement Model
+AV
+AV
+AV
V
V
V
V
V
RTS
RBS
REF
V
RT
RB
IN
S
S
S
16
18
19
20
21
22
23
24
25
26
28
27
29
17
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
®
Reference
Generator
Supply
Clock
+
Figure 1. ADC-321 Functional Block Diagram
Comparator
Comparator
Sampling
Sampling
Lower
Upper
4-Bit
4-Bit
A
B
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
TEST
+DV
TEST
A/D CLOCK
NO CONNECTION
NO CONNECTION
CLAMP IN (CLP)
+AV
FUNCTION
Encoder
Encoder
Lower
Upper
D-FF
4-Bit
4-Bit
A
B
S
S
INPUT/OUTPUT CONNECTIONS
(Analog)
(Digital)
Email: sales@datel.com
Video A/D Converter
Lower
Upper
Latch
Latch
Data
Data
PIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTION
NO CONNECTION
DIGITAL GROUND (DGND)
OUTPUT ENABLE (OE)
CLAMP ENABLE (CLE)
DIGITAL GROUND (DGND)
CLAMP CONTROL (COP)
CLAMP REF. (V
REF. BOTTOM SENSE (V
REF. BOTTOM (V
ANALOG GROUND (AGND)
ANALOG GROUND (AGND)
ANALOG IN (V
+AV
+AV
REF. TOP (V
REF. TOP SENSE (V
30 OUTPUT ENABLE
31 DGND
1
2
3
4
5
6
7
8
12 A/D CLOCK
15 CLAMP IN
9
10 +DV
11 TEST (Open)
8-Bit, 50MHz
S
S
ADC-321
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
TEST (Open)
(Analog)
(Analog)
Internet: www.datel.com
S
RT
IN
)
REF
)
RB
)
)
RTS
)
RBS
)

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adc-321 Summary of contents

Page 1

... CMOS/TTL compatible inputs Outputs 3-state TTL compatible Surface mount package GENERAL DESCRIPTION The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub- ranging A/D converter. The ADC-321 achieves a sampling rate comparable to flash converters by employing a sub-ranging technique which uses multiple comparator blocks each containing a sample-and-hold amplifier. The ADC-321 can operate with either a single +5V or dual +5V and +3 ...

Page 2

... ADC-321 ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS Power Supply Voltage (+AV , +DV ) –0 Analog Input Voltage –0.5 to +AV IN Reference Input Voltage ( –0 Digital Input Voltage ( –0 Digital Output Voltage ( –0 FUNCTIONAL SPECIFICATIONS Typical 25° ...

Page 3

... TECHNICAL NOTES 1. The ADC-321 is a monolithic CMOS device. It should be handled carefully to prevent static charge pickup has separate power supply terminals +AV and 20) and +DV (pin 10) for the internal analog and digital S circuits recommended that both +AV powered from a single source ...

Page 4

... THEORY OF OPERATION (See Functional Block Diagram, Figure 1, and Timing Diagrams, Figure 2) 1. The DATEL ADC-321 is a 2-step parallel A/D converter featuring a 4-bit upper comparator group and two 4-bit lower comparator groups, each with built-in sample and hold. A reference voltage equal to the voltage between (V – ...

Page 5

... Figure 3. Typical Connection Diagram 5 ADC-321 N (N+3) C (N+3) UD (N+2) H (N+2) C (N+2) LD (N) S (N+3) H (N+3) LD (N+1) Internal Operation of the ADC-321 A/D CLOCK 0.1µF 0.1µF 0.1µF 74HC04 0.1µF +5V (D) 47µ BIT 1 (MSB) 7 BIT 2 6 BIT 3 5 BIT 4 ADC-321 ...

Page 6

... ADC-321 +5V ( ANALOG 10pF Figure 4-1. Clamp Not Used in Self Bias Mode +5V ( ANALOG IN 20 10µ 10pF +5V ( 20k 0.01µF Figure 4-3. Clamp Used in Self Bias Mode ANALOG IN Figure 4-5 ...

Page 7

... Ambient Temperature vs. Max. Sampling Rate F = 50MHz S fin = 1kHz, triangular wave input + – Ambient Temperature (°C) Figure 5: Typical Performance Curves 7 ADC-321 Analog Input Frequency vs. S/N + THD, Effective Bit F = 50MHz 2Vp 25° 0.01 0.1 ...

Page 8

... AGND 25 32 0.03 (0.8) 0.02 (0.5) ADC-321 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com Data sheet fax back: (508) 261-2857 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith ...

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