cx29610 Mindspeed Technologies, cx29610 Datasheet - Page 33

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cx29610

Manufacturer Part Number
cx29610
Description
Optiphytm - M622 Sts-12/4x Sts-3 Sonet/sdh Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet

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Part Number:
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CX29610
CX29610 Data Sheet
Table 1-4. Pin Definitions (7 of 16)
29610-DSH-001-C
MMode
MClk
MRW*
MRD*
MTS*
MCS*
MA[10]
MA[9]
MA[8]
MA[7]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
MA[0]
Pin Label
Processor Interface
Selection
Microprocessor
Clock
Microprocessor
Read/Write Control
Microprocessor Read
Control
Microprocessor
Transfer Start
Microprocessor Chip
Select
Microprocessor
Address Bus
Signal Name
Mindspeed Technologies
D15
D10
D12
No.
C10
A10
C11
B10
A11
C8
A7
D8
B7
C9
A8
B8
A9
B9
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
Microprocessor interface clock.
Selects the type of interface. A
logic 1 selects the Motorola
MPC860 mode; a logic 0 selects
the Mindspeed EBUS mode.
Frequencies may range from
8 to 33 MHz.
Microprocessor read/write control
when the Motorola MPC860 mode
is selected via the MMode pin.
Microprocessor write control when
operating in the Mindspeed EBUS
mode
Microprocessor read control when
operating in the Mindspeed EBUS
mode.
Microprocess transfer start when
operating in the Motorola MPC860
mode. Microprocessor address
latch when operating in the
Mindspeed EBUS mode.
When MCS* is set to a logic “0,”
the device is enabled for read and
write accesses. When MCS* is set
to a logic “1,” the device does not
respond to input signal transitions
on MClk, MRW*, MRD*, MTS*.
Additionally, when MCS* is set to a
logic “1,” the MAD[7:0] pins are in
a high-impedance state but the
MIntr* pin remains operational.
Address inputs for identifying the
register that will be accessed.
Mindspeed EBUS mode, only pins
[10:8] are used for the address and
pins [7:0] are unused. The lower 8
bits of the EBUS address are
multiplexed on the micro interface
data bus (MAD). See
and 5-6.
When operating in the
1.0 Product Description
Description
1.5 Logic Diagram
Figures 5-5
1-19

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