cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 37
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cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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Figure 2-1. CX28250 Transmitter Block Diagram
28250-DSH-002-C
Tx Clock
Tx Data
Interface
PECL
Select
Clock
Serial
PECL
NRZ
Data
2.0 Functional Description
This chapter describes the CX28250 architecture and functional blocks.
Figure 2-1
HEC for incoming ATM cells from the UTOPIA interface and inserts it into the
fifth octet of each cell. The result is formatted into SONET frames and converted
to serial data. One of three clock sources is used to synchronize the outgoing data
stream over the PECL interface.
Parallel
19.44 MHz
Rx Clock
155.52 MHz (external)
Serial
Mindspeed Technologies
to
shows the CX28250 transmit signal path. The CX28250 calculates the
Parallel
Data
Out
Overhead
Framer
Input
2
™
Gen.
ATM
Cell
UTOPIA
FIFO
500035_006
2-1
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