k7a803600m Samsung Semiconductor, Inc., k7a803600m Datasheet - Page 18

• Manufacturer Part Number: k7a803600m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803600M
K7A801800M
The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
APPLICATION INFORMATION
DEPTH EXPANSION
INTERLEAVE READ TIMING
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n]
WRITE
CS
A
ADV
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
n+1
Microprocessor
1
t
SS
Address
A1
Data
ADS
CLK
*Notes : n = 14 32K depth ,
tSH
t
WS
Bank 0 is selected by CS
t
LZOE
t
ADVS
16 128K depth ,
18 512K depth ,
t
t
WH
OE
A
[0:19]
Q1-1
CLK
(Refer to non-interleave write timing for interleave write timing)
t
Cache
Controller
ADVH
Address
2
, and Bank 1 deselected by CS
Q1-2
15 64K depth
17 256K depth
19 1M depth
256Kx36 & 512Kx18 Synchronous SRAM
Q1-3
A
[19]
- 18 -
t
CSS
t
AS
tHZC
2
Q1-4
A
A2
CS
CS
CLK
ADSC
WEx
OE
CS
[0:18]
Address Data
ADV
2
2
1
t
tCSH
AH
t
t
LZC
CD
512Kx18
SPB
SRAM
(Bank 0)
Bank 0 is deselected by CS
ADSP
I/O
Q2-1
A
[0:71]
[19]
Undefined
Q2-2
2
, and Bank 1 selected by CS
A
CS
CS
CLK
ADSC
WEx
OE
CS
[0:18]
Address Data
ADV
2
2
1
Q2-3
512Kx18
SPB
SRAM
(Bank 1)
Don t Care
ADSP
March 2000
Rev 6.0
2
Q2-4