w364m72v-essb ETC-unknow, w364m72v-essb Datasheet

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w364m72v-essb

Manufacturer Part Number
w364m72v-essb
Description
64mx72 Synchronous Dram
Manufacturer
ETC-unknow
Datasheet
64Mx72 Synchronous DRAM
FEATURES
* This product is under development, is not qualifi ed or characterized and is subject to
January 2005
Rev. 1
change or cancellation without notice.
High Frequency = 100, 125MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Ranges
Organized as 64M x 72
Weight: W364M72V-XSBX - TBD grams typical
Commercial, Industrial and Military Temperature
Area: 9 x 265mm
22.3
SAVINGS – Area: 66% – I/O Count: 55%
TSOP
11.9
White Electronic Designs
54
TSOP
11.9
Area = 800mm
54
2
= 2,385mm
TSOP
11.9
54
ACTUAL SIZE
TSOP
2
Discrete Approach
11.9
54
White Electronic Designs
2
W364M72V-XSBX
32
TSOP
11.9
1
54
BENEFITS
GENERAL DESCRIPTION
The 512MByte (4.5Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
512M bits. Each chip is internally confi gured as a quad-
bank DRAM with a synchronous interface. Each of the
chip’s 134,217,728-bit banks is organized as 8,192 rows
by 2,048 columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
I/O Count = 219 Balls
I/O Count: 9 x 54 pins = 486 pins
66% SPACE SAVINGS
Reduced part count from 9 to 1
Reduced I/O count
• 55% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
TSOP
11.9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
54
25
TSOP
11.9
54
W364M72V-XSBX
TSOP
11.9
54
TSOP
11.9
54
ADVANCED*

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w364m72v-essb Summary of contents

Page 1

... Programmable Burst length 1,2,4,8 or full page 8,192 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 64M x 72 Weight: W364M72V-XSBX - TBD grams typical * This product is under development, is not qualifi characterized and is subject to change or cancellation without notice. Area = 800mm SAVINGS – Area: 66% – I/O Count: 55% 11 ...

Page 2

... January 2005 Rev. 1 W364M72V-XSBX The 4.5Gb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access ...

Page 3

... CCQ CCQ 3 W364M72V-XSBX CCQ CCQ ...

Page 4

... DQM DQMH WE# RAS# CAS 0-1 CLK IC4 CKE CS# DQM White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED WE# RAS# CAS 0-1 CLK 0 IC5 CKE 0 # CS# 0 DQM WE# RAS# CAS# ...

Page 5

... Be cause the Mode Register will power unknown state, it should be loaded prior to applying any operational command. January 2005 Rev. 1 W364M72V-XSBX REGISTER DEFINITION MODE REGISTER The Mode Register is used to defi ne the specifi c mode tion of the SDRAM. This defi nition includes the ...

Page 6

... Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-9, A11 select the unique column to be accessed, and Mode Register bit M3 is ignored. 6 W364M72V-XSBX TABLE 1 – BURST DEFINITION Order of Accesses Within a Burst Starting Column Address ...

Page 7

... When the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED DON'T CARE UNDEFINED T4 OH TABLE 2 – ...

Page 8

... tions already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-11 (A12 should be driven low). See Mode Reg is ter heading in the Register Defi ni tion sec tion. The LOAD MODE REGISTER January 2005 Rev. 1 W364M72V-XSBX CS# RAS# CAS# WE# DQM H X ...

Page 9

... AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not is sue another command to the same bank until the precharge January 2005 Rev. 1 W364M72V-XSBX time ( completed. This is determined explicit RP PRECHARGE com mand was issued at the earliest possible time ...

Page 10

... CAPACITANCE (NOTE 2) Symbol CI1 CA CI2 CIO BGA THERMAL RESISTANCE Symbol Theta JA Theta JB Theta JC 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED Unit V V °C °C °C Max Unit TBD pF TBD pF TBD pF TBD ...

Page 11

... CC CCQ A (All other pins not under test = 0V) CC ≤ V OUT CCQ +3.3V ± 0.3V; -55°C ≤ T ≤ +125°C CC CCQ A 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED Symbol Min Max 3.6 CC CCQ 0 ...

Page 12

... RCD t REF t REF t 70 RFC RRD t 0.3 T (23) 1 CLK + 7ns t WR (24 XSR 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED -125 Max Min Max ...

Page 13

... WRITE is executed. 24. Precharge mode only. 25. JEDEC and PC100 specify three clocks. 26. Parameter guaranteed by design. before going OH 27. Self refresh available in commercial and industrial temperatures only. 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED Symbol -100 -125 CCD ...

Page 14

... NOM 1.27 (0.050) NOM ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES January 2005 Rev. 1 Bottom View 32.1 (1.264) MAX 219 x Ø 0.762 (0.030) NOM 19.05 (0.750) NOM 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W364M72V-XSBX ADVANCED 25.1 (0.988) H ...

Page 15

... SB = 219 Plastic Ball Grid Array (PBGA), 32mm x 25mm DEVICE GRADE Mil i tary dus tri Com mer cial Blank = No temperature range specifi ed for 'ES' Non-qualifi ed product. Note 1: W364M72V-ESSB is only available product until completion of qualifi cation. January 2005 Rev. 1 ORDERING INFORMATION W 3 64M XXX -55° ...

Page 16

... SDRAM Multi-Chip Package, 32mm x 25mm Revision History Rev # History Rev 0 Initial Release Rev 1 Changes (Pg. 1, 5-15) 1.1 Added additional product data January 2005 Rev. 1 W364M72V-XSBX Release Date May 2004 January 2005 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com ADVANCED Status Advanced Advanced ...

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