lc8905v Sanyo Semiconductor Corporation, lc8905v Datasheet - Page 12

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lc8905v

Manufacturer Part Number
lc8905v
Description
Digital Audio Interface Receiver
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD)
1. Data input and output addresses are allocated as follows:
2. The input command codes control the following settings:
• System stop
• Data input pin settings
• Input bi-phase data output selection
• Validity flag output selection
• Audio data output format setting
DI1: Stops VCO operation and thus stops the system.
DI2: Selects which input data to demodulate.
DI3 and DI4: Select the E/DOUT pin output.
DI5 and DI6: Set the audio data output format.
All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used.
Data input
C bit output
Subcode Q, ID output
Data demodulation input
Data input or output
DATAOUT
E/DOUT
System
DI1
DI2
DI3
DI4
DI5
DI6
data output
16-bit right- 20-bit right-
Emphasis
MSB first
justified
L
L
Operating
F7
F8
F9
DIN1
L
L
L
L
flag output
Figure 2: Microprocessor Interface Timing 1
LSB first
justified
Validity
B0
1
0
1
H
H
B1
1
0
0
data output
20-bit right-
DIN1 input
MSB first
B2
justified
1
0
0
L
L
B3
Stopped
0
1
1
DIN2
LC8905V
H
H
H
H
data output
DIN2 input
A0
20-bit left-
1
1
1
MSB first
justified
H
H
A1
1
1
1
A2
1
1
1
A3
1
1
1
EA
E9
E8
Figure 3: Microprocessor Interface Timing 2
B0
0
1
0
B1
1
0
0
B2
0
0
0
B3
1
1
1
A0
0
0
0
A1
1
1
1
No. 5237-12/16
A2
1
1
1
A3
1
1
1

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