lc8902 Sanyo Semiconductor Corporation, lc8902 Datasheet - Page 9

• Manufacturer Part Number: lc8902
• Description: Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

2. Data output mode setting
3. System stop
Microcomputer Interface Output
Bits D0 to D15 in the microcomputer interface output format have the following meanings.
Interpretation of the D1 and D2 bits
Note: 1. The “#1” value indicates either a PLL lock error or analog source mode. In these states the data is cleared and bits D0 and D3 to D15 are all set to low.
D13 to D15
D5 to D12
Sampling frequency
Note: Setting the data demodulation input code to one of the XSYS settings switches the system clock from the VCO to the crystal oscillator and sets
There are two data output modes: 16-bit MSB first and 20-bit MSB first. These are selected by the bit I14 code.
The operation of both the VCO and the crystal oscillator can be stopped, thus stopping the whole LC8902/Q system,
by setting the bit I4 code as shown in the table.
The values of the bits I4 to I14 are all initialized to low immediately after the XMODE pin goes from low to high.
Since bits I0 to I3 and I15 are not used, their initial values are undefined.
2. D1 and D2 are in the “#1” state in the initial values of the codes immediately after the XMODE pin goes from low to high. All other codes are set to low.
3. The interval between one microcomputer data read out operation and the next must be 6 ms or longer.
D0
D1
D2
D3
D4
Data demodulation input
Bit
Data output mode
the LC8902/Q to analog source mode. Selecting one of the input pins once again sets the LC8902/Q to digital source mode and PLL operation.
D1
D2
DOUT1
DOUT2
I10
I11
I12
I13
I14
—
I5
I6
I7
I8
I9
I4
Invalid bit. Always output as a low level.
Indicates the sample frequency.
Corresponds to the fs external output pin.
Indicates the state of the copy flag.
High = copy enabled, low = copy protect
Outputs the first bit of the channel status bits.
These pins output the channel status 8-bit category codes serially.
Invalid bits. Always output as low levels.
32 kHz
H
H
DIN1
DIN1
DIN1
L
L
L
L
L
L
L
L
L
System operation
16-bit MSB first
DIN2
DIN2
DIN2
44.1 kHz
H
H
H
L
L
L
L
L
L
L
L
Function
L
L
DIN3
DIN3
DIN3
H
H
H
L
L
L
L
L
L
48 kHz
H
L
DIN4
DIN4
DIN4
H
H
H
H
H
H
L
L
L
LC8902, 8902Q
20-bit MSB first
System stop
DIN5
DIN5
DIN5
H
H
H
L
L
L
L
L
L
#1
H
L
H
H
XSYS
GND
GND
H
H
H
H
H
H
L
L
L
XSYS
GND
GND
H
H
H
H
H
H
L
L
L
XSYS
GND
GND
H
H
H
H
H
H
H
H
H
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