lc897194 Sanyo Semiconductor Corporation, lc897194 Datasheet - Page 10

• Manufacturer Part Number: lc897194
• Description: Cd-rom Decoder With Built-in Atapi Ide And Dvd Ecc Interfaces
• Manufacturer: Sanyo Semiconductor Corporation

3. Buffer RAM Pins
4. Subcode Interface Pins
5. CD DSP Data Pins
6. DVD ECC interface pins
7. Other Pins
IO0 to IO15 (input/output)
RA0 to RA9 (output)
ZRAS0, ZRAS1 (ZCS0, ZCS1) (output)
ZCAS0, ZCAS1 (output)
ZOE (output)
ZUWE, ZLWE (output)
WFCK, SCOR (input)
BCK, SDATA, LRCK, C2PO (input)
DRESP (input)
HDB0 to HDB7 (input)
DREQ (output)
ZRESET (input)
XTALCK, XTAL
MCK (output)
MCK2 (output)
ZRSTIC (output)
ZRSTCPU (output)
Data bus for the buffer DRAM. Pull-up resistors are built in.
Buffer RAM address pins.
Buffer DRAM RAS output pins. Although ZRAS0 is used normally, in applications that use two 1M (64K 16
bits) DRAMs, the ZRAS0 and ZRAS1 signals can be connected to each of DRAM RAS pins.
Buffer DRAM CAS output pins. Although ZCAS0 is used normally, in applications that use two-CAS DRAMs,
the ZCAS0 can be connected to the DRAM UCAS pin, and ZCAS1 to the DRAM LCAS pin.
The buffer DRAM read output pin.
Buffer DRAM write output signals. Connect these pins to the corresponding pins on the DRAMs.
When two-CAS DRAMs are used, connect ZLWE to the write enable signal.
Subcode interface pins. By connecting these pins to the CD DSP, the subcode sync can be detected and the CD
main channel buffering can be started according to that sync. Subcode data buffering and ECC are not
performed.
Connect these pins to the CD DSP to acquire the CD-ROM data.
C2PO is the C2 flag pin.
DVD ECC data is latched on the falling edge of this signal.
DVD ECC data input pins.
DVD ECC data request output.
The LC897194 reset pin. The LSI is reset when a low level is applied.
Applications must hold this pin low for at least 1 µs when power is first applied.
These pins drive an external crystal at either 16.9344 MHz or 33.8688 MHz.
An external clock frequency can also be input to the XTALCK pin.
Outputs either the XTALCK frequency or that frequency divided by 2. This output can be stopped.
Outputs either the XTALCK frequency or that frequency divided by 2 (with the opposite phase of the MCK pin)
or the XTALCK frequency divided by 512. This output can be stopped.
This pin can be set to output a low level by either setting bit 7 in the microcontroller register R46 (ZSYSRES)
low (0), or setting the ZHRST pin (pin 103) low. This pin output is in the high-impedance state when both
ZSYSRES and ZHRST are high.
Since this pin has an open-drain circuit, an external pull-up resistor must be provided.
A low-going pulse of about 1 ms (when XTALCK = 34 MHz, or about 2 ms when XTALCK = 16 MHz) is
generated on this pin when an ATAPI soft reset command (08H) is received.
An interrupt is issued to the microcontroller at this time. If the ZRESET pin (pin 77) is functioning with active-
low logic, the ZRESET signal is output without change to ZRSTCPU.
Since this pin has an open-drain circuit, an external pull-up resistor must be provided.
LC897194
No. 5572-10/11