k4x56323pi-wr000 Samsung Semiconductor, Inc., k4x56323pi-wr000 Datasheet - Page 4

• Manufacturer Part Number: k4x56323pi-wr000
• Description: 8m X32 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X56323PI - 7(8)E/G
7. Input/Output Function Description
RAS, CAS, WE
DQS0,DQS1,
DQS2,DQS3
DM0,DM1,
DM2,DM3
BA0, BA1
Symbol
A [n : 0]
CK, CK
VDDQ
VSSQ
CKE
VDD
VSS
DQ
CS
NC
Supply
Supply
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
-
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buff-
ers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all
functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and
CKE , are disabled during power-down and self refresh mode which are contrived for low standby power con-
sumption.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include
dummy loading internally, to match the DQ and DQS loading. For the x32, DM0 corresponds to the data on
DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, DM3
corresponds to the data on DQ24-DQ31
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE com-
mand is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRE-
CHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
determines which mode register( mode register or extended mode register ) is loaded during the MODE REG-
ISTER SET command.
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data.
it is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to
the data on DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corresponds to the data on
DQ24-DQ31
No Connect : No internal electrical connection is present.
DQ Power Supply : 1.7V to 1.95V
DQ Ground.
Power Supply : 1.7V to 1.95V
Ground.
- 7 -
Description
Mobile DDR SDRAM
June 2007