k4x56163pe-lg Samsung Semiconductor, Inc., k4x56163pe-lg Datasheet - Page 33

• Manufacturer Part Number: k4x56163pe-lg
• Description: 16m X16 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X56163PE-L(F)G
AC Timming Parameters & Specifications
Clock cycle time
Row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Active delay
Last data in to Read command
Col. address to Col. address delay
Clock high level width
Clock low level width
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
DQS write postamble time
Refresh interval time
Mode register set cycle time
Power down exit time
Auto refresh cycle time
Exit self refresh to active command
Data hold from DQS to earliest DQ edge
Clock half period
Parameter
CL=3.0
CL=3.0
256Mb
tWPRES
tWPREH
Symbol
tDQSQ
tDQSS
tDQSH
tWPST
tCDLR
tRPRE
tDQSL
tPDEX
tARFC
tSRFX
tRPST
tDIPW
tMRD
tRAS
tRCD
tRRD
tCCD
tDSC
tDAL
tSAC
tREF
tWR
tQH
tCK
tRC
tRP
tCH
tDS
tDH
tHP
tCL
tIS
tIH
33
1*tCK +tIS
tCLmin or
tWR+tRP
tHPmin -
tCHmin
1.0ns
0.45
0.45
0.75
0.25
Min
120
2.0
0.9
0.4
0.4
0.4
0.9
1.5
1.5
1.1
1.1
2.2
7.8
0.4
10
80
50
30
30
15
15
80
1
1
0
2
DDR200
Max
0.55
0.55
1.25
7.0
0.7
1.1
0.6
0.6
0.6
1.1
0.6
1*tCK +tIS
tCLmin or
tWR+tRP
Mobile-DDR SDRAM
tHPmin -
tCHmin
1.0ns
0.45
0.45
0.75
0.25
Min
120
0.9
0.9
1.5
1.5
7.8
2.0
0.4
0.4
0.4
2.0
2.0
3.0
0.4
15
90
60
30
30
15
30
80
1
1
0
2
DDR133
Max
0.55
0.55
1.25
7.0
0.9
1.1
0.6
0.6
0.6
1.1
0.6
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
-
March 2004
Note
5,6
5,6
1
2
3
1
4
1
1