M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet - Page 21

• Manufacturer Part Number: M25P128-VMF6G
• Description: 128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M25P128
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
Table 7.
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Signal
W
Table 2: Protected Area
1
0
1
0
SRWD
Bit
0
0
1
1
Protection Modes
Protected
Hardware
Protected
Software
(HPM)
(SPM)
Mode
Sizes.
Table
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Write Protection of the
2. The Write Status Register (WRSR) instruction also allows
Status Register
Rev. 1
Figure
12.
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected Area
Table 7
Memory Content
(1)
Ready to accept
Page Program and
Sector Erase
instructions
Ready to accept
Page Program and
Sector Erase
instructions
Unprotected Area
Instructions
W
) is
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