FM24C64C-G RAMTRON [Ramtron International Corporation], FM24C64C-G Datasheet
FM24C64C-G
Related parts for FM24C64C-G
FM24C64C-G Summary of contents
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... SOIC (-G) Pin Configuration caused by VSS Pin Names A0-A2 SDA SCL WP VSS VDD Ordering Information FM24C64C-G FM24C64C-GTR 1850 Ramtron Drive, Colorado Springs, CO 80921 VDD SCL 3 6 SDA 4 5 Function Device Select Address Serial Data/address Serial Clock ...
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... Write access is permitted to the lower three- quarters of the address space. When WP is low, all addresses may be written. This pin is pulled down internally. VDD Supply Supply Voltage: 5V VSS Supply Ground Rev. 1.1 June 2011 Address Latch Figure 1. FM24C64C Block Diagram FM24C64C 1,024 x 64 FRAM Array 8 Data Latch ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24C64C due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... If the receiver acknowledges the last byte, this will cause the FM24C64C to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. ...
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... After the address information has been transmitted, data transfer between the bus master and the FM24C64C can begin. For a read operation, the FM24C64C will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C64C will transfer the next sequential byte ...
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... Current Address & Sequential Read The FM24C64C uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation ...
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... Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C64C, a row is 64 bits wide. Every 8-byte boundary marks Rev. 1.1 June 2011 set ...
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... DD Min Typ 4.5 5.0 4 -0 other inputs -0. Stop command issued FM24C64C Ratings -1.0V to +7.0V -1.0V to +7.0V and V < V +1. -55 125C 260 C 2.5kV 1.25kV 100V MSL-1 Max Units Notes 5 A 100 A 200 A 400 ...
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... DD Max Units min 4.5V to 5.5V unless otherwise specified) DD min) DD waveform. DD FM24C64C Max Min Max Units Notes 400 0 1000 kHz s 0.6 s 0.4 s 0.9 0.55 s 0.5 s 0.25 s 0. 100 ns 300 300 ns 1 300 100 ...
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... 0 HIGH 1/fSCL t AA Stop Start t HD:DAT t t SU:DAT HD:STA Stop Start Min FM24C64C Equivalent AC Load Circuit 5.5V 1700 Output 100 LOW t HD:DAT t SU:DAT t DH Acknowledge t AA Acknowledge Max Units Notes - Years ...
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... SOIC Package Marking Scheme Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM24C64C, “Green” SOIC package, Year 2010, Work Week 47 FM24C64C-G A00002G1 RIC1047 Rev. 1.1 June 2011 Recommended PCB Footprint 3.90 0.10 6.00 0.20 ± ...
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... Revision History Revision Date 1.0 3/22/2011 1.1 6/30/2011 Rev. 1.1 June 2011 Summary Initial Release Added ESD ratings. FM24C64C ...