IDT71V3578 IDT [Integrated Device Technology], IDT71V3578 Datasheet - Page 9

• Manufacturer Part Number: IDT71V3578
• Description: 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. All values are maximum guaranteed values.
2. At f = f
3. For I/Os V
NOTE:
1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Symbol
Symbol
I
I
I
SB1
SB2
I
DD
ZZ
|I
V
V
|I
|I
LZZ
LO
OL
OH
LI
|
|
|
MAX,
Operating Power Supply
Current
CMOS Standby Power
Supply Current
Clock Running Power
Supply Current
Full Sleep Mode Supply
Current
HD
inputs are cycling at the maximum frequency of read cycles of 1/t
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
ZZ, LBO and JTAG Input Leakage Current
= V
DDQ
Parameter
- 0.2V, V
LD
= 0.2V. For other inputs V
Parameter
Device Selected, Outputs Open, V
Device Deselected, Outputs Open, V
Device Deselected, Outputs Open, V
V
V
V
ZZ > V
DDQ
DDQ
DDQ
= Max., V
= Max., V
= Max., V
HD,
V
DD
See Figure 1
(1)
= Max.
IN
IN
IN
0 to 3V
1.5V
1.5V
Test Conditions
> V
> V
> V
HD
2ns
IH
HD
HD
= V
or < V
or < V
or < V
DD
DD
5301 tbl 10
I
I
V
V
V
OL
OH
and the ZZ pin will be internally pulled to V
- 0.2V, V
DD
DD
OUT
IL
LD
LD
= +8mA, V
= -8mA, V
, f = f
= Max., V
= Max., V
, f = 0
, f = f
= 0V to V
6.42
DD
CYC
MAX
DD
DD
9
LD
MAX
= Max.,
(2,3)
(2)
= Max.,
= Max.,
while ADSC = LOW; f=0 means no input lines are changing.
(Typical, ns)
= 0.2V.
DD
(2,3)
DD
IN
IN
DDQ
= 0V to V
= 0V to V
= Min.
= Min.
, Device Deselected
tCD
Test Conditions
Figure 2. Lumped Capacitive Load, Typical Derating
DD
DD
200MHz
Com'l
6
5
4
3
2
1
360
130
30
30
Commercial and Industrial Temperature Ranges
20 30 50
Com'l
I/O
340
120
30
30
SS
183MHz
if they are not actively driven in the application.
Capacitance (pF)
80
Figure 1. AC Test Load
Ind
350
130
35
35
100
Z
0
= 50
Min.
2.4
Com'l
___
___
___
___
320
110
30
30
166 MHz
50
Max.
0.4
30
___
330
5
5
Ind
120
V
35
35
DDQ
5301 drw 06
5301 drw 07
5301 tbl 08
5301 tbl 09
/2
200
Unit
µ A
µ A
µ A
Unit
mA
mA
mA
mA
V
V
,
,