IDT71V67703 IDT [Integrated Device Technology], IDT71V67703 Datasheet - Page 7

• Manufacturer Part Number: IDT71V67703
• Description: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. R5 does not have to be directly connected to V
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M devices CS
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
0
will be removed, B2 will be used for address expansion.
M
C
D
G
H
N
U
A
B
E
K
P
R
F
L
T
J
M
C
D
G
H
N
U
A
B
E
K
P
R
F
L
T
J
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
1
I/O
I/O
I/O
NC
I/O
NC
NC
NC
NC
NC
NC
NC
16
17
20
22
24
25
29
31
DDQ
DDQ
DDQ
DDQ
DDQ
1
11
13
15
8
SS
DNU
as long as the input voltage is < V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CS
NC
A
A
A
DNU
2
I/O
DD
I/O
I/O
I/O
V
CS
I/O
A
6
7
P3
P4
5
NC
NC
NC
NC
NC
18
19
21
23
26
27
28
30
A
A
A
0
2
DD
10
(3)
(4)
6
7
10
12
14
P2
5
9
0
(3)
(4)
DNU
V
V
V
BW
V
V
BW
V
V
V
LBO
A
A
A
A
NC
DNU
3
SS
SS
SS
SS
SS
SS
SS
SS
BW
10
V
V
V
V
V
V
V
V
V
LBO
A
4
3
2
A
A
A
NC
3
3
4
SS
SS
SS
SS
SS
SS
SS
SS
SS
15
(3)
4
3
2
2
(3)
ADSC
ADSP
DNU
6.42
BWE
ADV
CLK
V
V
V
GW
A
NC
NC
CE
OE
A
A
ADSC
ADSP
DNU
4
DD
DD
DD
BWE
11
ADV
CLK
V
V
V
GW
1
0
NC
NC
NC
7
CE
OE
A
A
4
DD
DD
DD
(3)
1
0
(3)
IL
DNU
.
BW
BW
V
V
V
V
V
V
V
V
V
A
A
NC
A
A
DNU
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
12
14
BW
V
V
V
V
V
V
V
V
V
A
V
A
8
9
NC
A
A
2
1
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
13
SS
14
(3)
(1)
8
9
1
(3)
(1)
DNU
I/O
I/O
I/O
I/O
I/O
V
A
A
I/O
I/O
I/O
I/O
I/O
A
NC
A
DNU
Commercial and Industrial Temperature Ranges
6
DD
I/O
16
15
13
17
A
A
I/O
I/O
V
I/O
I/O
A
A
P2
NC
NC
NC
NC
NC
13
12
11
A
P1
9
6
4
3
2
6
DD
16
17
12
11
18
(3)
P1
6
4
2
1
(3)
5309 drw 02c
5309 drw 02d
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
7
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
I/O
NC
ZZ
15
14
10
DDQ
DDQ
DDQ
DDQ
DDQ
8
7
5
1
(2)
0
7
7
5
3
(2)
0
,