NJU26109 NJRC [New Japan Radio], NJU26109 Datasheet - Page 15

• Manufacturer Part Number: NJU26109
• Description: NJU26100 Series Hardware Specification
• Manufacturer: NJRC [New Japan Radio]

5.2 I
host interface transfers data to the SDA pin and clocks data to the SCL pin. SDA is an open drain pin requiring an
external 4.7k pull-up resistor. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial
host interface. This offers additional flexibility to a system design by four different SLAVE addresses of the
NJU26100 Series. An address can be arbitrarily set up by the AD1, 2 pins. The I
connection of AD1, 2 pins. The I
described in the each data sheet. Refer to the each data sheet.
* It excepts NJU26150. Refer to each data sheet.
*1 The SLAVE address bit is 0 when ADx-pin is low level. The SLAVE address bit is 1 when ADx-pin is high level.
START condition, followed by the SLAVE address byte. The SLAVE address consists of the seven-bit SLAVE
address followed by a read/write (R/W) bit. When an address with an effective serial host interface is detected, the
acknowledgement bit which sets a SDA line to Low in the ninth bit clock cycle is returned.
the transfer. R/W = 0 indicates the host will send to the NJU26100 Series while R/W = 1 indicates the host will
receive data from the NJU26100 Series.
Ver.2005-02-24
When the NJU26100 Series is configured for I
The figure on the following page shows the basic timing relationships for transfers. A transfer is initiated with a
The R/W bit in the SLAVE address byte sets the direction of data transmission until a STOP condition terminates
In case of the NJU26100 Series, only single-byte transmission is available.
The serial host interface supports “Standard-Mode (100kbps)” I
bit7
0
2
C Bus
bit6
0
SDA
SCL
bit5
1
Start
S
Table 5-3 I
2
C address should be the same level of AD1, 2 pins. The real I
Address
1-7
bit4
1
Fig. 5-2 I
2
C Bus SLAVE Address
R/W
8
2
C bus communication in GPIO0 pin (*SEL1 pin)=”Low”, the serial
bit3
1
ACK
9
2
C Bus Format
1-7
bit2
AD2*
Data
2
C bus data transfer.
1
8
bit1
AD1*
ACK
9
1
2
Stop
C address of AD1, 2 is decided by
P
bit0
R/W
2
C address is
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