IDT72251 IDT [Integrated Device Technology], IDT72251 Datasheet - Page 5

• Manufacturer Part Number: IDT72251
• Description: CMOS SyncFIFOO 8192 X 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72251 CMOS SyncFIFO
8192 x 9
SIGNAL DESCRIPTIONS
INPUTS:
CONTROLS:
(
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (
(
Programmable Almost-Empty Flag (
after t
zeros and the offset registers are initialized to their default
values.
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (
Programmable Almost-Full Flag (
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
coincident.
programmable flags, Write Enable 1 (
enable control pin. In this configuration, when Write Enable 1
(
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
the input register holds the previous data and no new data is
allowed to be loaded into the register.
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
allowing a valid write to begin. Write Enable 1 (
ignored when the FIFO is full.
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
coincident.
RS
PAF
WEN1
Data In (D
Reset (
Write Clock (WCLK) — A write cycle is initiated on the
The write and read clocks can be asynchronous or
Write Enable 1 (
In this configuration, when Write Enable 1 (
If the FIFO is configured to have two write enables, which
To prevent data overflow, the Full Flag (
Read Clock (RCLK) — Data can be read on the outputs on
The write and read clocks can be asynchronous or
) input is taken to a LOW state. During reset, both internal
) will be reset to HIGH after t
RSF
) is low, data can be loaded into the input register and
. During reset, the output register is initialized to all
RS RS
EF
) — Reset is accomplished whenever the Reset
0
) and Programmable Almost-Empty Flag (
- D
8
) — Data inputs for 9-bit wide data.
WEN1
WEN1
FF
) and Programmable Almost-Full Flag
) — If the FIFO is configured for
RSF
FF
PAF
) will go HIGH after t
. The Empty Flag (
PAE
) are synchronized with
) will be reset to LOW
WEN1
FF
WEN1
) will go LOW,
) is the only
WEN1
) is HIGH,
FF
EF
) and
PAE
) and
WFF
) is
)
,
5.14
(
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
output register holds the previous data and no new data is
allowed to be loaded into the register.
Flag (
a valid write operation has been accomplished, the Empty
Flag (
The Read Enables (
is empty.
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (
(HIGH), the Q output data bus is in a high-impedance state.
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth
expansion. If Write Enable 2/Load (WEN2/
Reset (
pin.
Write Enable (
LD
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
and/or Write Enable 2/Load (WEN2/
register holds the previous data and no new data is allowed to
be loaded into the register.
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (
allowing a valid write to begin. Write Enable 1 (
Enable 2/Load (WEN2/
the Write Enable 2/Load (WEN2/
(
registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.
the Write Enable 1 (
LD
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
REN1
RS
Read Enables (
When either Read Enable (
When all the data has been read from the FIFO, the Empty
Output Enable (
Write Enable 2/Load (WEN2/
If the FIFO is configured to have two write enables, when
In this configuration, when Write Enable (
To prevent data overflow, the Full Flag (
The FIFO is configured to have programmable flags when
If the FIFO is configured to have programmable flags when
) is HIGH, data can be loaded into the input register and
) are set low, data on the inputs D is written into the Empty
=low).
EF
EF
,
RS
REN2
) will go LOW, inhibiting further read operations. Once
) will go HIGH after t
= LOW), this pin operates as a second write enable
The IDT7225 device contain four 8-bit offset
) are LOW, data is read from the RAM array to
WEN1
REN1
REN1
WEN1
REN1
) is LOW and Write Enable 2/Load (WEN2/
OE OE
LD
) — When Output Enable (
,
REN2
REN2
,
) and Write Enable 2/Load (WEN2/
) are ignored when the FIFO is full.
REN2
REF
COMMERCIAL TEMPERATURE RANGES
) — When both Read Enables
FF
REN1
L L D D
) are ignored when the FIFO
and a valid read can begin.
LD
) will go HIGH after t
) — This is a dual-purpose
) is set LOW at Reset
LD
,
REN2
) is LOW, the input
LD
FF
WEN1
OE
WEN1
) is HIGH, the
) will go LOW,
) is set high at
) is disabled
) and Write
) is HIGH
OE
WFF
5
) is
,