IDT72V01 IDT [Integrated Device Technology], IDT72V01 Datasheet - Page 5

• Manufacturer Part Number: IDT72V01
• Description: 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
AC TEST CONDITIONS
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
CONTROLS:
RESET (
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
Read Enable (
the high state during the window shown in Figure 2, (i.e.,
t
until t
will be reset to high after Reset (
WRITE ENABLE (
Full Flag (
adhered to with respect to the rising edge of the Write Enable
(
independently of any on-going read operation.
the next write operation, the Half-Full Flag (
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
reset by the rising edge of the read operation.
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from
in
READ ENABLE (
Enable (
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (
RSS
W
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
W
Data inputs for 9-bit wide data.
Reset is accomplished whenever the Reset (
A write cycle is initiated on the falling edge of this input if the
).
After half of the memory is filled and at the falling edge of
To prevent data overflow, the Full Flag (
A read cycle is initiated on the falling edge of the Read
before the rising edge of
will not affect the FIFO when it is full.
RSR
Data is stored in the RAM array sequentially and
R
RS RS
) provided the Empty Flag (
FF
after the rising edge of
)
0
) is not set. Data set-up and hold times must be
– D
R R
) and Write Enable (
8
R R
)
W W
)
)
RS RS
) and should not change
FF
RS RS
RS RS
W
EF
) will go high after t
W W
).
, so external changes
. Half-Full Flag (
) is not set. The data
) inputs must be in
GND to 3.0V
See Figure 1
HF
FF
1.5V
1.5V
5ns
) will be set to
R
) will go low,
) goes high,
RS
HF
) input is
) is then
2679 tbl 08
RFF
HF HF
)
,
5.08
the Data Outputs (Q
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped-
ance state. Once a valid write operation has been accom-
plished, the Empty Flag (
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (
transmit data when the Retransmit Enable control (
is pulsed low. A retransmit operation will set the internal read
pointer to the first location and will not affect the write pointer.
Read Enable (
state during retransmit. This feature is useful when less than
512/1024/2048/4096 writes are performed between resets.
The retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Half-Full Flag (
pending on the relative locations of the read and write point-
ers.
EXPANSION IN (
grounded to indicate an operation in the single device mode.
Expansion In (
previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (
eration, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (
This is a dual-purpose input. In the Depth Expansion Mode,
The IDT72V01/72V02/72V03/72V04 can be made to re-
This input is a dual-purpose pin. Expansion In (
The Full Flag (
OUTPUT
FF FF
XI
* Includes scope and jig capacitances.
R
) and Write Enable (
) is connected to Expansion Out (
)
XI XI
PIN
FF
TO
680
)
Figure 1. Output Load
) will go low, inhibiting further write op-
0
or equivalent circuit
– Q
EF
COMMERCIAL TEMPERATURE RANGE
8
) will go high after t
) will return to a high impedance
R
XI
so external changes in
FL FL
).
RS
5.0V
/
RT RT
), the Full-Flag (
1.1K
30pF*
)
W
) must be in the high
2679 drw 03
EF
WEF
) will go low,
and a valid
XO
FF
RT
R
HF
) will go
) of the
will not
) input
), de-
XI
5
) is