IDT72V3656 IDT [Integrated Device Technology], IDT72V3656 Datasheet - Page 28

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IDT72V3656

Manufacturer Part Number
IDT72V3656
Description
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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NOTES:
1. t
2. If Port C size is word or byte, t
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
C0-C17
A0-A35
WENC
CLKA edge is less than t
CLKC
CLKA
W/RA
SKEW1
MBC
MBA
CSA
EFA
ENA
FFC
is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
t
t
ENS2
ENS2
FIFO2 Empty
LOW
HIGH
t
LOW
LOW
DS
Write 1
SKEW1
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
t
DH
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
DS
Write 2
t
SKEW1
t
t
t
ENH
DH
ENH
(1)
t
CLKH
1
t
CLK
t
CLKL
28
TM
2
t
CLKH
t
t
ENS2
REF
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
4665 drw20

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