IDT74SSTU32864 IDT [Integrated Device Technology], IDT74SSTU32864 Datasheet - Page 9

• Manufacturer Part Number: IDT74SSTU32864
• Description: 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
• Manufacturer: IDT [Integrated Device Technology]

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
NOTES:
1. This parameter is not production tested.
2. Data and V
3. Data, V
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. For reference only. Final values to be determined.
4. This parameter is not production tested.
5. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
IDT74SSTU32864/A
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
Symbol
t
INACT (1,3)
t
f
ACT (1,2)
CLOCK
t
dV/dt_∆
t
Symbol
PDMSS
tw
SU
t
dV/dt_r
H
dV/dt_f
t
PDM
t
f
RPHL
MAX
(2)
REF
(2,4)
(5)
, and clock inputs must be held at valid levels (not floating) a minimum time of t
REF
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup Time
Hold Time
inputs must be low a minimum time of t
Parameter
CLK and CLK to Q
CLK and CLK to Q (simultaneous switching)
RESET to Q
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
DCS before CLK↑, CLK↓, CSR HIGH
DCS before CLK↑, CLK↓, CSR LOW
DODT, CSR, Data, and DCKE before CLK↑, CLK↓
Data, DCS, CSR, DCKE, and DODT after CLK↑, CLK↓
ACT
max, after RESET is taken HIGH.
9
(1)
1.41
Min
270
—
—
—
1
1
INACT
(3)
max, after RESET is taken LOW.
V
DD
= 1.8V ± 0.1V
Min.
0.7
0.5
0.5
0.5
—
—
—
1
V
DD
= 1.8V ± 0.1V
2.15
2.35
Max.
—
3
4
4
1
COMMERCIAL TEMPERATURE RANGE
(3)
(3)
Max.
TBD
TBD
270
—
—
—
—
—
MHz
Unit
V/ns
V/ns
V/ns
ns
ns
ns
MHz
Unit
ns
ns
ns
ns
ns