IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 21

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

3.4
is used to divide the clock frequency down to the internal DPLL’s
required input frequency, which is no more than 38.88 MHz.
the corresponding IN_FREQ[3:0] bits are ‘0000’). The 8 kHz clock is
extracted from the composite clock and the Pre-Divider is bypassed
automatically.
sponding IN_FREQ[3:0] bits.
IN5 and IN6 also include an HF (High Frequency) Divider. Figure 3
shows a block diagram of the pre-dividers for an input clock and Table 3
shows the Pre-Divider Functions.
8 kHz internally; the PRE_DIVN_VALUE [14:0] bits are not required.
Lock 8k Divider can be used for 1.544 MHz, 2.048 MHz, 6.48 MHz,
19.44 MHz, 25.92 MHz or 38.88 MHz input clock frequency and the cor-
responding IN_FREQ[3:0] bits should be set to match the input fre-
quency.
is bypassed by setting IN3_DIV[1:0] bits / IN4_DIV[1:0] bits = 0,
DIRECT_DIV bit = 0, and LOCK_8k bit = 0. The corresponding
IN_FREQ[3:0] bits should be set to match the input frequency. The input
clock can be inverted, as determine by the IN_2K_4K_8K_INV bit.
used when the input clock is higher than (>) 155.52 MHz. The input
clock can be divided by 4, 5 or can bypass the HF Divider, as deter-
mined by the IN5_DIV[1:0]/IN6_DIV[1:0] bits correspondingly.
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
Functional Description
IDT82V3380A
Input Clock INn
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e.,
For IN3 ~ IN14, the DPLL required frequency is set by the corre-
Each Pre-Divider consists of a DivN Divider and a Lock 8k Divider.
When the Lock 8k Divider is used, the input clock is divided down to
For 2 kHz, 4 kHz or 8 kHz input clock frequency only, the Pre-Divider
The HF Divider, which is only available for IN5 and IN6, should be
Either the DivN Divider or the Lock 8k Divider can be used or both
(3 < n < 14)
INPUT CLOCK PRE-DIVIDER
Pre-Divider
(for IN5 & IN6 only)
HF Divider
IN5_DIV[1:0] bits / IN6_DIV[1:0] bits
Figure 3. Pre-Divider for An Input Clock
1
0
21
setting should observe the following order:
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
less than or equal to (≤) 155.52 MHz.
on the input clock on one of the IN3 ~ IN14 pins and the DPLL required
clock. Here is an example:
clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN6
to ‘0010’. Do the following step by step to divide the input clock:
When the DivN Divider is used for INn (3 ≤ n ≤ 14), the division factor
Once the division factor is set for the input clock selected by the
The DivN Divider can only divide the input clock whose frequency is
The Pre-Divider configuration and the division factor setting depend
The input clock on the IN6 pin is 622.08 MHz; the DPLL required
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
3. Write the higher eight bits of the division factor to the
1. Use the HF Divider to divide the clock down to 155.52 MHz:
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
PRE_DIVN_VALUE[7:0] bits;
PRE_DIVN_VALUE[14:8] bits.
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
622.08 ÷ 155.52 = 4, so set the IN6_DIV[1:0] bits to ‘01’;
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN6_CNFG to ‘1’ and the
LOCK_8K bit in Register IN6_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Lock 8k Divider
2 < N < 19440
DivN Divider
SYNCHRONOUS ETHERNET WAN PLL™
00
10
01
DIRECT_DIV bit
LOCK_8K bit
DPLL clock
May 16, 2011