tcd2561d TOSHIBA Semiconductor CORPORATION, tcd2561d Datasheet - Page 11

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tcd2561d

Manufacturer Part Number
tcd2561d
Description
Toshiba Ccd Linear Image Sensor Ccd Charge Coupled Device
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Timing Requirements
Clamp Mode
Changeover Switch Mode
Pulse timing of SH and f1
SH pulse rise time, fall time
SH pulse width
Pulse timing of SH and CP
Pulse timing of SH and CP
(line clamp mode)
Pulse timing of SH and SW
f1, f2 pulse rise time, fall time
Pulse timing of RS and CP
Pulse timing of f
Reference level settle time
(bit clamp mode)
Video data delay time
Reference level settle time
(line clamp mode)
Note 12: Typ. is the case of f
Note 13: Line clamp Mode inside ( ).
Note 14: Load Resistance is 100 kW.
Note 15: Typical settle time to about 1% of final value.
Note 16: Typical settle time to about 1% of the peak.
Clamp Means
RS pulse rise time, fall time
RS pulse width
CP pulse rise time, fall time
CP pulse width
Output Type
Line Clamp
Bit Clamp
Color
B/W
Characteristics
1A
, f
SW
2A
CP Input Pulse
“H” or SH
and CP
CP Pulse
1
Input Pulse
“H”
“L”
(Note 13)
(Note 14)
(cont.)
RS
= 1.0 MHz.
Symbol
t11, t12
t16, t17
t9, t10
t2, t4
t13
t14
t15
t18
t19
t20
t21
t1
t5
t3
t6
t7
t8
SW
2
Input Pulse
“H”
“L”
30 (3000)
10 (20)
3000
Min
120
800
200
100
10
¾
¾
¾
0
0
0
0
0
0
11
80 (5000)
(Note 12)
1000
1000
5000
Typ.
500
100
500
50
50
20
80
40
20
20
20
20
30
40 (Note 16)
40 (Note 15)
50 (Note 16)
t3 - 100
Max
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCD2561D
2001-12-06

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