icx434 Sony Electronics, icx434 Datasheet
icx434
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icx434 Summary of contents
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... Base oscillation frequency 48.6/36.0MHz • Electronic shutter function • Supports draft, AF mode • H/V driver for CCD Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors • ICX432 (Type 1/2.7, 3240K pixels) • ICX434 (Type 1/3.2, 2020K pixels) Pin Configuration ...
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Block Diagram OSCI 28 OSCO 27 CKI 26 1/2 MCKO 30 25 CKO SNCSL 3 Selector SSI 31 SCK 32 Register SEN 33 SSGSL 6 RST 2 TEST1 18 TEST2 CKG 1/2 ...
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Pin Description Pin Symbol I/O No — GND SS Internal system reset input. 2 RST I Normally apply reset during power-on. Control input used to switch sync system. 3 SNCSL I Vertical direction line identification pulse output/exposure ...
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... CCD vertical register clock output/V3B for ICX434 CCD vertical register clock output/open for ICX434. 44 V3A O CCD vertical register clock output//V1A for ICX434 — –7.5V power supply. (Power supply for vertical driver) 46 V3B O CCD vertical register clock output/V1B for ICX434. ...
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Electrical Characteristics DC Characteristics Item Pins Supply voltage Supply voltage Supply voltage RST, SSI, 1 Input voltage 1 SCK, SEN TEST1, TEST2, ...
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Inverter I/O Characteristics for Oscillation Item Pins Symbol Logical Vth OSCI LVth V Input voltage OSCI V V Output voltage OSCO V Feedback OSCI, RFB resistor OSCO Oscillation OSCI, f frequency OSCO Inverter Input Characteristics for Base Oscillation Clock Duty ...
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Switching Waveforms V1 (V3A, V3B, V5A, V5B) V2 (V4, V6) SUB Waveform Noise VCLH TTMH TTHM 90% 90% TTLM 10% 10% 90% 90% 10% TTLM 90% 90% 10% TTLH TTHL 90% 90% 10% VCMH VCML VCLL – 7 – CXD3615R ...
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Measurement Circuit VR HR +3.3V –7.5V +15. C1: 3300pF C2: 560pF R1: ...
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AC Characteristics AC characteristics between the serial interface clocks SSI 0.2V DD SCK SEN 0. SEN Symbol t s1 SSI setup time, activated by the rising edge of SCK t h1 SSI hold time, activated by the rising ...
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Serial interface clock internal loading characteristics ( 0. ts1 0. SEN Be sure to maintain a constantly high SEN logic level near the falling edge of VR. Symbol t SEN setup time, activated ...
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RST loading characteristics RST Symbol t w1 RST pulse width VR and HR phase characteristics VR HR Symbol setup time, activated by the falling edge hold time, activated by the falling edge ...
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Description of Operation Pulses output from the CXD3615R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following ...
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Serial Interface Control The CXD3615R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HR. Here, readout portion specifies the horizontal period during which V1, V3A/B and ...
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... See the OBCLP waveform pattern section. See the ADCLK logic phase section. See the standby section. — — – 14 – CXD3615R Data = 1 RST Enabled All 0 Disabled 0 All — — 0 PAL 0 ICX434 0 — All — 0 FLD EXP All 0 All 0 All ...
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Shutter Data Data Symbol Function D00 to CHIP Chip enable D07 D08 CTG Category switching D09 — D10 Electronic shutter vertical period to SVR specification D19 D20 Electronic shutter horizontal period to SHR specification D31 D32 High-speed shutter position to ...
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... Test mode 1 These are both test mode for the ICX434. Draft mode is the pulse elimination drive mode in the ICX432/434. AF mode is the pulse eliminator drive mode based on draft mode, and is a high frame rate drive mode that can be used for purposes such as auto focus (AF). ...
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... SLP Sleep mode 1 0 SST Siesta mode 1 1 STB Standby mode See the Pin Status Table for the pin status in each mode. ICX432 ICX434 (Normal (Shifted rearward (Shifted forward (Wide – ...
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Control data/shutter data: [Electronic shutter] The CXD3615R realizes various electronic shutter functions by using control data D20 SMD and D21 HTSG and shutter data D10 to D19 SVR, D20 to D31 SHR and D32 to D41 SPL. These functions are ...
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VR SHR V3A SUB WEN EXP SMD SVR SHR Exposure time Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is ...
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... This is shown below. Frame mode [ICX432] Draft/AF mode Frame mode [ICX434] Draft mode See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation ...
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... Application Circuit Block Diagram CCD CCD OUT ICX432 ICX434 V5A 40 V5B V3A 44 V3B SUB 48 V1 and V2 only for ICX432 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same ...
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Package Outline Unit: mm 9.0 ± 0.2 7.0 ± 0 0.5 + 0.08 0.18 – 0.03 0˚ to 10˚ DETAIL A SONY CODE EIAJ CODE JEDEC CODE 48PIN LQFP (PLASTIC (0.22) 12 ...