lxt9781 Intel Corporation, lxt9781 Datasheet - Page 23

• Manufacturer Part Number: lxt9781
• Description: Fast Ethernet 10/100 Multi-port Transceiver With Rmii
• Manufacturer: Intel Corporation

2.2.1.2
2.2.2
2.2.3
2.2.3.1
Datasheet
impedance is high enough that it has no practical effect on the external termination circuit. On the
transmit side, Intel’s patented waveshaping technology shapes the outgoing signal to help reduce
the need for external EMI filters. Four slew rate settings (refer to
designer to match the output waveform to the magnetic characteristics.
Fiber Interface
The LXT97x1 provides a PECL interface that complies with the ANSI X3.166 specification. This
interface is suitable for driving a fiber-optic coupler.
Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control
Interface or MDIO registers.
RMII Interface
The LXT97x1 provides a separate RMII for each network port, each complying with the RMII
standard. The RMII includes both a data interface and an MDIO management interface.
Configuration Management Interface
The LXT97x1 provides both an MDIO Management interface and a Hardware Control interface
(via the LED/CFG pins) for device configuration and management. Mode control selection is
provided via the MDDIS pin as shown in
MDIO Management Interface
The LXT97x1 supports the IEEE 802.3 MII Management Interface also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and
control the state of the LXT97x1. The MDIO interface consists of a physical connection, a specific
protocol that runs across the connection, and an internal set of addressable registers. Some
registers are required and their functions are defined by the IEEE 802.3 specification. Additional
registers allow for expanded functionality. Specific bits in the registers are referenced using an
“X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used. The timing for the MDIO Interface is shown in
page
The protocol allows one controller to communicate with multiple LXT97x1 chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number (0 through 5 for the
LXT9761, or 0 through 7 for the LXT9781) to the base address to obtain its port address as shown
in
MII Addressing
Figure
60. MDIO read and write cycles are shown in
6.
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Table
1.
Figure 7
(read) and
Table 5 on page
Figure 8
(write).
17) allow the
Table 30 on
23