la72700v Sanyo Semiconductor Corporation, la72700v Datasheet
la72700v
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la72700v Summary of contents
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... Ordering number : ENA0015 LA72700V Overview LA72700V MTS (Multi Channel Television Sound) decoder. Features • With SIF circuit, STEREO channel separation is alignment-free. • Built-in filters are adjustment free. • SAP output level is selectable 2 levels. • Included control function for STEREO and SAP detection sensitivity. ...
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... STEREO S/N ratio SNS STEREO separation 1 STSE1 STEREO separation 2 STSE2 STEREO Detection level-1 VINSD1 STEREO Detection level-2 VINSD2 LA72700V Conditions Conditions No signal Inflow current at pin 31 * Default condition fc = 4.5MHz Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) ±25kHz 100% Modulation MONO(L+R): 530mVp-p (300Hz, Pre-emphasis ON) ...
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... Normally measurement condition is Input = SIF mode (-90dBµV), ALC = OFF * " Reference " Items are reference levels, their specs are no-guarantee. Package Dimensions unit : mm 3247B LA72700V Conditions Input Mod. Difference at Stereo /Except Stereo Det default condition Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT ...
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... Block Diagram and Application Circuit Example LA72700V No.A0015-4/16 ...
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... LA72700V Condition 0 0 Stereo Prohibit 0 Normal (Auto det) 1 Forced Mono Normal (MUTE off) MUTE ALC off (Through) ALC on SAP LEVEL-1 SAP LEVEL-2 SIF mode ...
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... Pin Functions DC voltage No. Pin function AC level 1 PC_DC_IN DC: 3.8V AC: 2.4Vp-p 2 PC_DCOUT DC: 3.8V AC: 2.4Vp-p 3 PCSTFILT DC: 3.8V 4 PCPLDET DC: 3.8V 5 PISIF DC: 3.7V LA72700V Input/output form AC coupling (Input) AC coupling (Output) Stereo VCO PLL filter Pilot level detect Signal input Reference Continued on next page. No.A0015-6/16 ...
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... Continued from preceding page. DC voltage No. Pin function AC level 6 GND CSAPDET DC: 2. FIL DC: 2.9V 10 MUTE DC SDA 12 SCL LA72700V Input/output form SAP carrier level detect No connect SIF offset cancel MUTE = 5V Serial data input Serial clock input Reference Continued on next page. No.A0015-7/16 ...
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... PSTSENS DC: 3.1V 15 PSAPSENS DC: 3.1V 16 PCTNWID DC: 4.0V 17 PCDETWID DC: 3.8V LA72700V Input/output form Offset cancel filter Stereo det sensitivity change OPEN = default Insert resistor(30k or over) = Low sensitivity SAP detect sensitivity control OPEN = default controlled by insert resistor * see electrical reference dbx RMS detect(wide band) dbx wide detect Reference Continued on next page ...
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... DC: 3.8V 20 PCSPECIN DC: 3.8V 21 PCDOSPE DC: 3.8V AC: 220mVp-p 22 PCDBXOUT DC: 3.8V AC: 220mVp-p 23 PCDBX_IN LA72700V Input/output form dbx spectral detect 18 5kΩ OMP05019 dbx RMS detect (Spectral band) dbx main signal V/I convert filter Offset cancel filter AC coupling (Output) AC coupling (Input) Reference Continued on next page. No.A0015-9/16 ...
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... Continued from preceding page. DC voltage No. Pin function AC level 24 PCALCFIL DC: 0.6V 25 PORCH DC: 3.8V AC: 1.4mVp-p 26 POLCH DC: 3.8V AC: 1.4mVp-p 27 PCREG DC: 3.8V LA72700V Input/output form ALC filter * When ALC function no-use, this terminal is open. Line out R Line out L Reference Voltage Reference Continued on next page. No.A0015-10/16 ...
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... AC level 28 PMAIN_IN DC: 3.5V AC: 220mVp-p 29 PMAINOUT DC: 3.8V AC: 220mVp-p 30 PCREG76 DC: 1. POLED DC* * See Mode table 33 PICLKFSC DC: 0V AC* * 200mVp-p Recommend LA72700V Input/output form AC coupling (Input) AC coupling (Output) Regulator Mode out MONO = 0.9V SAP = 2.0V STEREO = 3.0V STEREO+SAP = 3.8V Fsc input 3.579545MHz, 200mVp-p Reference Continued on next page. No.A0015-11/16 ...
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... Continued from preceding page. DC voltage No. Pin function AC level 34 PCDJFIL DC: 2.5V 35 PCPLC DC: 6.3V 36 PCPLC2 DC: 6.3V LA72700V Input/output form Filter adjustment signal detect Pilot canceller reference-1 Pilot canceller reference-2 Reference No.A0015-12/16 ...
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... Output 5bits data as follows; bit8 is result of STERO DET (H: STEREO) bit7 is result of SAP DET (H: SAP) bit6 to bit1 are fixed to “L” LA72700V 2 C -BUS) with serial data, and controlled by two terminals which called SCL (serial *1 the condition of starting data transfer, and after that, input 8 bit data to *3 8th bit shows the direction of transferring data “ ...
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... Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time Data set-up time Set-up time for STOP condition BUS free time between a STOP and START condition Timing Chart LA72700V Symbol Min ...
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... Measurement Circuit LA72700V No.A0015-15/16 ...
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... SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2005. Specifications and information herein are subject to change without notice. LA72700V PS No.8340-16/16 ...