la72670bm Sanyo Semiconductor Corporation, la72670bm Datasheet - Page 19

• Manufacturer Part Number: la72670bm
• Description: Us Multiplex Modulation For Vcr Hifi Sound Signal Processor
• Manufacturer: Sanyo Semiconductor Corporation

I
(1) DATA TRANSFER MANUAL
(2) TRANSFER DATA FORMAT
data-1 means data for group-1, data-2 means data for group-2.
(3) INITIALIZE
START
Fig.1 DATA STRUCTURE “WRITE” mode
2
Condition
C BUS serial interface specification
This IC adopts control method(IIC-BUS) with serial data, and controlled by two terminals which called SCL(serial
clock) and SDA (serial data).At first, set up the condition of starting data transfer
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of
Bit),and save the order. The 9th bit takes ACK (ACKnowledge) period, during SCL terminal takes “H”, this IC pull
down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of data transfer stop
condition
As a part of transfer data write down to internal memory (V latch system), internal control
doesn’t change just after the transfer.
After transfer start condition, transfers slave address(1110100*) to SDA terminal, next, sub address(0000****),
control data
slave address transfer, transfer sub address(n)
Data works with all of the bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be
canceled only the data of group.
This LSI is initialized for circuit protection.
The initialization period is decided Pin 16 capacity value by internal impedance 15kΩ, and shown with
t = -CR×Ln(0.2). Data cannot be accepted for this period.
t = 530ms at C = 22µF, In this case, Please transmit data in consideration of the uneven after about 700ms.
*1 Defined by SCL rise down SDA during ‘H’ period.
*2 Defined by SCL rise up SDA during ‘H’ period.
*3 There are 1 to 5 groups.
*4 Pointed date by sub address becomes group No. of next control data.
*5 It is called R/W bit.
*2
Slave
, thus the transfer comes to close.
Address
*3
, then, stop condition(See figure 1). And this LSI have a auto address increment function, then, next of
R/W
L
*5
ACK Sub Address(n) ACK
*4
, group (n ) data, after that, group (n+1) and so on.
LA72670BM
Control data(n) ACK
control data(n+1) ACK
*1
, and after that, input 8 bit data to
…… STOP condition
PS No.A0644-19/20