cxd1947q Sony Electronics, cxd1947q Datasheet - Page 3

• Manufacturer Part Number: cxd1947q
• Description: Ieee1394 Link Layer / Pci Bridge Lsi
• Manufacturer: Sony Electronics

Functions
1. Asynchronous Function
defined 1394 packet formats. Packets to be transmitted
are read out of host memory and received packets are
written into host memory, both using DMA. CXD1947Q
can be programmed to act as a bus bridge between PCI
and 1394 by directly executing 1394 read and write
requests to the first 4GB of node offset address as read
and writes to PCI memory space. The CXD1947Q can
also be programmed to automatically place the data from
read response packets in the proper location in host
memory, then optionally interrupt the host processor to
indicate that the transaction is complete.
2. Isochronous Function
master function as defined by 1394. This means it con-
tains a cycle timer and counter, and can transmit a spe-
cial packet called a “cycle start” after every rising edge of
the 8KHz cycle clock. The CXD1947Q can either gener-
ate the cycle clock from the 49.152MHz clock it receives
from the PHY, or use the “CycleIn” pin directly. When not
the cycle master, the CXD1947Q keeps its internal cycle
timer synchronized with the cycle master node by cor-
recting its own cycle timer with the reload value from the
cycle start packet. The CXD1947Q supports two isochro-
nous transmit channels and two isochronous receive
channels. The CXD1947Q can regulate the rate of trans-
mit to emulate data rates which are synchronous with,
but not even multiples of, the 8KHz cycle clock.
3. PCI Interface
PCI bus. As a slave, it decodes and responds to access-
es to registers within CXD1947Q. As a master, it acts on
behalf of the DMA units to generate transactions on the
PCI bus. These transactions are used to move streams
of data between system memory and the devices, as
well as to read and write the DMA command lists.
4. DMA
nels: one Asynchronous Transmit channel, one
Asynchronous Receive channel, and four Isochronous
channels. The CXD1947Q also has Physical DMA capa-
bility to respond to incoming requests to physical
The CXD1947Q can transmit and receive all of the
The CXD1947Q is capable of performing the cycle
This block acts both as a master and a slave on the
The CXD1947Q supports six independent DMA chan-
–3–
addresses. The DMA unit is made up of three controller
modules which support these various DMA functions.
Each module has access to the PCI Interface to perform
move operations, and is capable of sequencing through
buffer descriptor lists stored in main memory in order to
find the next buffer address after a channel exhausts the
previous buffer. This frees the system from stringent
interrupt response requirements after buffer completions.
gram pointers and the current context for each of its
DMA channels. A 32-bit incrementer updates both the
Channel Program Pointers and the current buffer point-
ers. A 16-bit decrementer is used to adjust the count val-
ues for the channels. These incrementers and
decrementers will be shared if a Controller unit has multi-
ple channels.
5. Miscelleneous Functions
cally turns off the asynchronous transmitter. The receiver
remains on so that the CXD1947Q can receive PHY self-
ID packets during the self-ID process which immediately
follows the 1394 bus reset.
receives the new node ID from the PHY and updates its
node ID register. Host system software must explicitly
restart the transmitter, presumably after it has corrected
the node addresses of any queued-up packets.
Semiconductor Silicon Serial Number™ chip. This inter-
face retrieves a unique serial number which manage-
ment software then uses to uniquely identify the node for
which the CXD1947Q is attached on the 1394 interface.
6. Brief Hardware Description
nections in a host system. The CXD1947Q attaches to
the host via PCI bus. PCI provides an inexpensive and
moderatly high performance point for the connection of
I/O devices. PCI is a 32-bit, multiplexed address/data
bus, capable of performing 32-bit transfers at a rate of
33MHz.
Each DMA controller stores the current channel pro-
Upon detecting a bus reset, the CXD1947Q automati-
Following the bus reset operation, the CXD1947Q
The CXD1947Q has an interface to a Dallas
The block diagram shows the CXD1947Q and its con-
Preliminary
CXD1947Q