LS110GXS-1CF269I LATTICE [Lattice Semiconductor], LS110GXS-1CF269I Datasheet - Page 13

• Manufacturer Part Number: LS110GXS-1CF269I
• Description: Fully Integrated 10Gbps Serializer/Deserializer Device
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Configuration Pin Descriptions
Transmitter Controls
TX_D_EN
TX_LV_PLLBPb
TX_FIFO_INIT
TX_CML_ISET[1:0]
TX_CK622_PA[1:0]
RESET_TXb
PWDN_TXb
TX_CK_LV_SEL
TX_CK_LV_PA[1:0]
TX_CP_ISET[1:0]
Receiver Controls
RX_REF_CK_ENb
RX_LV_CKDLY[1:0]
Pin Name
1
TX_CK_LV_SEL = 1/16
TX_CK_LV_SEL = 1/32
State
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
1
0
1
0
1
0
1
0
1
0
1
0
1
0
th
nd
of Frequency
of Frequency
TX_D_P/N output is active
TX_D_P/N output is inactive.
The internal LVDS PLL is active
The internal LVDS PLL is bypassed. External clock management and
phase adjustment is required when this pin is 0.
Initialize the TXFIFO
No action
See V
data sheet.
3T/4
Adjust T/2
Adjust T/4
No Adjust
Transmitter in normal operation
Resets the transmitter
Transmitter is operating
Transmitter is powered down
TX_CK_LV is 1/16 of frequency
TX_CK_LV is 1/32 of frequency
Clock delay = 0
Clock delay = -T/16
Clock delay = T/16
Clock delay = T/8
Clock delay = T/4
Clock delay = T/4-T/32
Clock delay = T/4+T/32
Clock delay = T/4+T/16
622MHz clock (default using internal pull-ups)
Invalid
Invalid
155MHz clock
RX_REF_CK is disabled
RX_REF_CK is enabled
LVDS output clock is delayed: 90ps
LVDS output clock is delayed: 180ps
LVDS output clock is delayed: 270ps
LVDS output clock is delayed: 360ps
2
OD
13
in the High Speed Input/Output Specifications section of this
Action
XPIO 110GXS Data Sheet