hm5118165tt-7 Elpida Memory, Inc., hm5118165tt-7 Datasheet - Page 13

• Manufacturer Part Number: hm5118165tt-7
• Description: 16 M Edo Dram 1-mword ? 16-bit
• Manufacturer: Elpida Memory, Inc.

20 All the V
21. t
22. t
23. t
24. t
25. t
26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold
28. Please do not use t
29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of
31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
32. XXX: H or L (H: V
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (t
specified t
page mode mix cycle (1) and (2).
When output buffer is turned on and off within a very short time, generally it causes large V
line noise, which causes to degrade V
time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between t
state from normal operation mode to self refresh mode. If t
should use t
refresh should be executed within 15.6 µs immediately after exiting from and before entering into
self refresh mode.
distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after
exiting from and before entering into the self refresh mode.
fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V
ASC
CRP
CWL
CP
HPC
is determined by the time that both UCAS and LCAS are high.
, t
, t
, t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
CAH
CHR
DH
, t
, t
, t
CC
DS
IH
OHR
RCS
RCH
HPC
and V
or V
and t
RPS
, t
, t
and t
(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO
WCS
CPA
instead of t
IL
.
SS
CSH
, t
and t
OH
IH
pins shall be supplied with the same voltages.
RASS
WCH
should be satisfied by both UCAS and LCAS.
(min)
, and between t
, t
CPW
timing, 10 µs
CSR
Data Sheet E0154H10
RP
are determined by the later rising edge of UCAS or LCAS.
V
and t
.
IN
V
RPC
IH
OFR
(max), L: V
are determined by the earlier falling edge of UCAS or LCAS.
IH
t
and t
RASS
min/V
OFF
100 µs. During this period, the device is in transition
IL
.
max level.
IL
(min)
CAS
V
IN
+ t
RASS
CP
V
IL
+ 2 t
100 µs, then RAS precharge time
(max))
T
) becomes greater than the
HM5118165 Series
CC
/V
SS
13