w89c926 Winbond Electronics Corp America, w89c926 Datasheet - Page 24

• Manufacturer Part Number: w89c926
• Description: Pcmcia Ethernet Network Twisted Pair Interface Controller
• Manufacturer: Winbond Electronics Corp America

BUS ARBITRATION AND STATE DIAGRAM
The PENTIC+ handles bus arbitration automatically. It can operate in four modes: idle state, slave
read/write mode, DMA mode, and shared memory mode. The PENTIC+ controls the on-board
devices by decoding these modes.
At power-on, the PENTIC+ is in idle mode. If a register read/write command is issued, the PENTIC+
enters the slave read/write mode. If a local DMA or remote DMA (I/O mode only) is initiated by the
PENTIC+ core coprocessor, the PENTIC+ enters DMA mode. A memory command will place the
PENTIC+ in memory mode. At any given time, the PENTIC+ can be in only one state. The PENTIC+
handles state changes automatically. However, two events, such as a DMA command and a memory
command, may be requested at the same time; in this case, the PENTIC+ allocates the bus on a first-
come, first-served basis. No predefined priority is set within the PENTIC+.
In cases where the system has no authority on the requested bus, the PENTIC+ will drive the WAIT
pin low so that the system can insert wait states. After the PENTIC+ has released the bus authority,
SLCT CORE FUNCTION
The SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register
files, transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks
is depicted in the following block diagram.
WAIT is deasserted to instruct the system to stop inserting wait states.
PCMCIA
Slot
Interface
Reset
Power-on
DMA
Interface
Logic
Idle
Register
access
Core
access
Memory
access
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Register
File
16-byte
FIFO
W89C926 PENTIC+
DMA operation
Slave read/ write
Memory operation
Transmit
Receive
Logic
Logic
TX/RX
SNA
Logic