w89c840af Winbond Electronics Corp America, w89c840af Datasheet - Page 45

• Manufacturer Part Number: w89c840af
• Description: 100/10mbps Ethernet Controller
• Manufacturer: Winbond Electronics Corp America

21
20
19:16
15:14
R/W
R/W
R
R/W
WAIT
DBE
---
CA
Wait State Insertion
When WAIT is set, the W89C840AF, as a bus master, executes
memory read/write with one wait state every data phase. When
WAIT is reset, the W89C840AF, as a bus master, executes
memory read/write with zero wait state every data phase.
Descriptor Big Endian Mode
When set, the descriptors will be handled in big endian mode;
when reset, the descriptors will be treated in little endian mode
Reserved. Fixed at 0.
Cache Alignment
CA defines the address boundary for the burst access to the
transmission or receive data.
When the starting address of the data burst access is not aligned,
more specifically, the starting address should be a multiple of
some number such as 4, 8 etc., the W89C840AF will have the
first burst transfer that causes that the next burst access will has
the start address aligned.
After the first burst occurred, all other burst operation are
aligned with the configuration of CA accordingly.
The CA must be initialized with a non zero value after reset.
The alignment configuration is as following:
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[15:14]
[00]
[01]
[10]
[11]
-45 -
8 long-word alignment
16 long-word alignment
32 long-word alignment
Address Alignment
reserved
Publication Release Date:October 2000
Revision 1.01
W89C840AF