cxd2460r Sony Electronics, cxd2460r Datasheet
cxd2460r
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cxd2460r Summary of contents
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... Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2460R developed to generate the timing pulses required by Progressive Scan CCD image sensors as well as signal processing circuits. Features • Electronic shutter function • Supports non-interlaced operation • Base oscillation frequency 28.636MHz • ...
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... XSGA and XSGB are readout pulses that use V2A and V2B, respectively, as the VH value Pulse Generator – 2 – CXD2460R V-Driver 15 XCPDM 21 PBLK 22 XCPOB EXP 28 TEST2 47 DSGAT ...
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... V2B 44 SUB DSGAT The enclosed pins use separate power supplies. – 3 – CXD2460R RST ADCLK 23 22 XCPOB 21 PBLK XRS XSHD 18 17 XSHP 16 AVD2 15 XCPDM 14 AVD1 ...
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... PS = Low: Serial setting clock input High: Shutter speed setting input. 31 SSI Low: Serial setting data input Line identification signal output write enable pulse output or XSUB output. 33 EXP O Pulse output indicating exposure is underway or checksum result output. Description – 4 – CXD2460R ...
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... CCD electric charge sweep pulse output — –8.0V power supply (vertical clock driver power supply). 47 DSGAT I Output stop (Same operation control as SLP when low). Parallel/serial switching for mode setting input method (High: Parallel, Low: Serial) With pull-down resistor. Description – 5 – CXD2460R ...
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... OM7 OH Pull-in current where I = 10.0mA V OL7 OL V Feed current where I = –7.2mA OM101 OH V Pull-in current where I = 5.0mA OL OM102 V Feed current where I = –5.0mA OH OL8 Pull-in current where I = 10.0mA V OL8 OL – 6 – CXD2460R Min. Typ. Max. Unit 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 5.0 5.25 V 3.0 3.3 3.6 V 14.5 15.0 15.5 V — 0.0 — ...
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... OH V Pull-in current where I = 6.0mA OL OL RFB Vss (Within the recommended operating conditions) Symbol Conditions LVth fmax 50MHz sine wave IN Conditions – 7 – CXD2460R Min. Typ. Max. Unit a/2 DD 500k ...
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... Measurement Circuit TTMH TTHM 90% 90% TTLM TTML 10% 10% 90% 90% 10% 10% TTLM TTML 90% 90% 10% 10% TTHL TTLH 90% 90% 10% 10% VCMH VCLL V2A V2B R1 – 8 – CXD2460R VCML VH VL R1: 27 R2: 5 C1: 1500pF C2: 3300pF ...
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... XSGA pulse to 300ns from the falling edge of HRI immediately after generation of XSGA pulse th1 ts1 a DD ts3 0.8V DD ts2 th2 (Within the recommended operating conditions) Definition 0.5V DD – 9 – CXD2460R 0. Min. Typ. Max. Unit 7. 300ns ...
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... FRI and HRI hold time, activated by the rising edge of MCK twRST 0. tpRST Definition 0. tsSYNC thSYNC 0. (Within the recommended operating conditions) Definition – 10 – CXD2460R 0. 0. Min. Typ. Max. Unit 125 0. Min. Typ. Max. ...
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... Time until the WEN, ID and EXP outputs change after the tpdEXP fall of MCK Time until the FRO and HRO outputs change after the fall tpdSYNCO of MCK 0. 0. tpdEXP 0. tpdSYNCO (Within the recommended operating conditions) Definition – 11 – CXD2460R Min. Typ. Max. Unit 0.5 8.5 ns 0.5 3.5 ns ...
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... CCD drive pulse generation is synchronized with HRI and FRI. • The CCD drive method can be changed to various modes by inputting serial data or parallel data to the CXD2460R. • The various drive methods possessed by the CXD2460R are shown in the Timing Charts A rate) and B rate). 2. Serial data input method • ...
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... Serial data and description of functions The serial interface data is loaded to the CXD2460R when D00 and D07 are "1". However, this D00 assumes that D40 to D47 CHKSUM is satisfied. to D07 D06 D05 D04 D03 D02 D01 D00 D07 CHIP This CTGRY data indicates the functions that the serial interface data controls. ...
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... Y line (example) Sweep variable period (period X) Effective signal period (period Y) Sweep fixed period (period Z) Timing chart FRI Z X V2A 69H Set by FVFS (Fix) D16 to Set to "0". D17 Detailed description Reset by FRI after normal transfer Y – 14 – CXD2460R 1068 ...
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... Operation control settings The operating mode control bits are loaded to the CXD2460R at the rise timing of the SEN input, and control is applied immediately. D19 D18 Symbol 0 0 CAM 0 1 SLP 1 X STN Pin status during operation control Pin Symbol CAM SLP No. ...
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... The setting range is from "0" to "31". When set to "0", readout operation is performed at the first FR. to When this bit is invalid. D29 VSHUT MSB D29 D28 D27 D26 D25 D30 Invalid data to D39 CXD2460R clock system When using a 28.636MHz crystal FHIGH FINE Mode1 1 1 Mode2 1 0 Mode3 0 0 Note) Combinations of FHIGH and FINE other than those listed above are prohibited ...
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... Input "0". to D39 High-speed and low-speed electronic shutter can be used together. Therefore, the exposure time is as follows: FR cycle VSHUT + (fv – HSHUT) Detailed description LSB HR cycle + 634/MCK frequency [Hz] = Exposure time [s] – 17 – CXD2460R Function Number of SUB pulses setting (fv: Number 1FR) ...
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... Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO. 1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low. D12 Note that the STB setting has priority. Set SGXEN to "1" in the case of input of a CXD2460R SGXEN sync signal from the outside. ...
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... Serial data is loaded to the internal registers only when checksum is OK. Data is not reflected to the registers if checksum is NG. Also, when CHKSUM = 0, the checksum results are always OK and the data is reflected to the registers. Detailed description Detailed description LSB CHKSUM If the total = 0, the checksum results are OK. – 19 – CXD2460R ...
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... Shutter speed setting specifications when When the CXD2460R can be controlled without inputting serial data by using the SEN, SSK and SSI pins. Pin FHIGH (horizontal drive SEN Serial register FHIGH = 0. frequency) FINE Serial register FINE = 0 and the SSK (readout method) CXD2460R operates in DRAFT mode ...
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... DSGAT DSGAT is ON when low and the CXD2460R is set to sleep mode as with SLP of STB. Note that control is applied when either or both of DSGAT and SLP are ON. Also, when STN is ON, the CXD2460R is set to standby mode regardless of the DSGAT status. ...
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... HRI FRI V2A SUB EXP MAX 6 (76 (76) MAX 6 (76 (76) Location where XSG is normally generated. (However, this pulse is not actually generated.) MAX 1 to MAX 6 (76 (76) Numbers in parentheses are for FS mode. – 22 – CXD2460R (76 (76 (76) ...
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... HSHUT = 0 (with low-speed electronic shutter) HSHUT value 1 to MAX 0 HRI FRI V2A SUB EXP 1 to MAX (with low-speed electronic shutter) 6 (76) MAX 0 6 (76 (76) 0 (with low-speed electronic shutter) 6 (76) Numbers in parentheses are for FS mode. – 23 – CXD2460R (76 (76 (76) ...
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... CXD2460R 1040 ...
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... CXD2460R – 25 – 0/267 1 5 0/267 1 5 ...
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... CXD2460R ...
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... CXD2460R ...
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... CXD2460R ...
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... CXD2460R ...
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... CXD2460R – 30 – 112 126 140 154 168 182 196 210 224 238 252 266 280 294 308 322 ...
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... CXD2460R ...
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... CXD2460R – 32 – 112 120 152 154 168 196 216 210 238 252 280 294 322 336 364 392 392 378 406 420 448 462 490 504 532 546 574 588 616 630 658 ...
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... Logical Phase 2MCK MCK XSHP XSHD XRS ADCLK – 33 – CXD2460R ...
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... Sensor ICX205AK For making FR and HR outside the CXD2460R, configure a circuit that counts MCK. (Using 2MCK, CKO, etc. is not recommended.) Also, set system setting data, SGXEN (D12) to "1" and stop a built-in SSG. Use crystal oscillator (fundamental wave) as base oscillation. Be sure to input duty 50% pulse when crystal oscillator is used ...
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... Notes on Turning Power ON To avoid setting VSUB pin of the CCD image sensor negative potential, the former two power supplies should be raised by the following order among three power supplies, VL and VH. t1 20% 20 – 35 – CXD2460R ...
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... EIAJ CODE JEDEC CODE 48PIN LQFP (PLASTIC (0.22 0.2 1.5 – 0.1 0.13 M 0.1 ± 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 36 – CXD2460R + 0.05 0.127 – 0.02 0.1 S EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g ...