SS8018TR SSC [Silicon Standard Corp.], SS8018TR Datasheet - Page 9

• Manufacturer Part Number: SS8018TR
• Manufacturer: SSC [Silicon Standard Corp.]

Rev.2.01 6/06/2003
Slave Address
The SS8018 appears to the SMBus as one device hav-
ing a common address for both ADC channels. The
SS8018 device address is set to 1001100.
The SS8018 also responds to the SMBus Alert Re-
sponse slave address (see the Alert Response Address
section).
One-Shot Register
The One-shot register is to initiate a single conversion and
comparison cycle when the device is in standby mode and
auto conversion mode. The write operation to this register
causes one-shot conversion and the data written to it is
irrelevant and is not stored.
Serial Bus Interface Reinitialization
When SMBCLK is held low for more than 30ms (typical)
during an SMBus communication, the SS8018 will reiniti-
ate its bus interface and be ready for a new transmission.
Alarm Threshold Registers
Four
high-temperature (T
registers for each A/D channel. If either measured tem-
perature equals or exceeds the corresponding alarm
threshold value, an
The power-on-reset (POR) state of both T
full scale (01010101, or +85 C). The POR state of both
T
Diode Fault Alarm
There is a fault detector at DXP that detects whether the
remote diode has an open-circuit condition. At the begin-
ning of each conversion, the diode fault is checked, and
the status byte is updated. This fault detector is a simple
voltage detector. If DXP rises above VCC – 1V (typical)
due to the diode current source, a fault is detected and
the device alarms through pulling
remote temperature reading doesn’t update in this condi-
tion. Note that the diode fault isn’t checked until a conver-
sion is initiated, so immediately after power-on reset the
status byte indicates no fault is present, even if the diode
path is broken.
If the remote channel is shorted (DXP to DXN or DXP to
GND), the ADC reads 1000 0000(-128 C) so as not to trip
either the T
LOW
registers is 0 C.
registers
HIGH
or T
store
LOW
ALERT
HIGH
alarms at their POR settings.
) and low-temperature (T
alarm
interrupt is asserted.
threshold data, with
ALERT
www.SiliconStandard.com
HIGH
low while the
registers is
LOW
)
The
only be cleared by reading the Alert Response address.
Interrupts are generated in response to T
comparisons and when the remote diode is discon-
nected (for fault detection). The interrupt does not halt
automatic conversions; new temperature data continues
to be available over the SMBus interface after
asserted. The interrupt output pin is open-drain so that
devices can share a common interrupt line. The interrupt
rate can never exceed the conversion rate.
The interface responds to the SMBus Alert Response
address, an interrupt pointer return-address feature (see
Alert Response Address section). Prior to taking correc-
tive action, always check to ensure that an interrupt is
valid by reading the current temperature.
Alert Response Address
The SMBus Alert Response interrupt pointer provides
quick fault identification for simple slave devices that
lack the complex, expensive logic needed to be a bus
master. Upon receiving an
host master can broadcast a Receive Byte transmission
to the Alert Response slave address (0001 100). Then
any slave device that generated an interrupt attempts to
identify itself by putting its own address on the bus (Ta-
ble 4).
The Alert Response can activate several different slave
devices simultaneously, similar to the SMBus General
Call. If more than one slave attempts to respond, bus
arbitration rules apply, and the device with the lower
address code wins. The losing device does not generate
an acknowledge and continues to hold the
low until serviced (implies that the host interrupt input is
level-sensitive). Successful reading of the alert response
address clears the interrupt latch.
Table 4. Read Format for Alert Response Address
(0001 100)
ALERT Interrupts
ALERT
7(MSB)
0(LSB)
BIT
6
5
4
3
2
1
interrupt output signal is latched and can
ALERT
interrupt signal, the
NAME
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
1
HIGH
SS8018
ALERT
and T
ALERT
9 of 14
line
LOW
is