74F525PCX NSC [National Semiconductor], 74F525PCX Datasheet - Page 3

• Manufacturer Part Number: 74F525PCX
• Description: Programmable Counter
• Manufacturer: NSC [National Semiconductor]

3
Functional Description
MODE 4 Interval Timer Pulse Output with Count Hold
While XTR is HIGH the data in the data latches is loaded
into the counter upon the next positive edge of CP The
negative edge of XTR enables the count-down to begin with
the next positive edge of CP When the count reaches zero
Q normally low is brought HIGH for a single period of CP
Q 2 toggles state on the positive edge of Q Taking XTR
HIGH before the counters reach zero stops the count-down
from the point where it was held Data cannot be reloaded
into the counter until a count of zero is reached See Figure
MODE 5 Interval Timer Inverted Pulse Output with
Count Hold
The operation is exactly the same as Mode 4 except that Q
is normally HIGH and goes LOW for a single period of CP
Q 2 toggles on the negative-edge of Q See Figure 3
Block Diagram
M
0
0
0
0
1
1
1
1
2
M
0
0
1
1
0
0
1
1
1
Function Table
M
0
1
0
1
0
1
0
1
0
(Continued)
Function
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
3
ure 4 NOTE that the pulse width of Q will be N-1 clock
Figure 5
MODE 6 Retriggerable Synchronous One-Shot
When XTR is HIGH the data in the data latches is loaded
into the counter upon the positive edge of CP The negative
edge of XTR enables the count-down to begin with the next
positive edge of CP wehre Q normally LOW is then
brought HIGH and the counter is decremented when the
count reaches zero Q is brought LOW and Q 2 is toggled
Bringing XTR HIGH during the count-down will allow the
data in the data latches to be loaded into the counter with
the next positive edge of CP but will not affect Q See Fig-
cycles where N is the number loaded into the counter
N
results
MODE 7 Frequency Generator
When XTR is HIGH the data in the data latches is loaded
into the counter upon the positive edge of CP The negative
edge of XTR enables the count-down to begin with the next
positive edge of CP When the count reaches zero Q nor-
mally LOW is brought HIGH for a single period of CP and
Q 2 is toggled The same clock edge that brings Q HIGH
also loads the data in the data latches into the counter The
counter will start to count on the next positive edge of CP
This mode will run continuously after an initial XTR until
stopped by MR Taking XTR HIGH at any time causes the
data in the data latches to be loaded into the counter and Q
output to be cleared with the next positive edge of CP See
e
1 should not be used as this may cause unpredictable
TL F 9547 – 4