in74hc112 Integral Corp., in74hc112 Datasheet

Manufacturer Part Number

in74hc112

Description

Dual J-k Flip-flop With Set And Reset

Manufacturer

Integral Corp.

Datasheet

1.IN74HC112.pdf (5 pages)

Dual J-K Flip-Flop

with Set and Reset

High-Performance Silicon-Gate CMOS

device inputs are compatible with standard CMOS outputs; with

pullup resistors, they are compatible with LS/ALSTTL outputs.

asynchronous Set and Reset inputs.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 μA

• High Noise Immunity Characteristic of CMOS Devices

The IN74HC112 is identical in pinout to the LS/ALS112. The

Each flip-flop is negative-edge clocked and has active-low

LOGIC DIAGRAM

PIN 8 = GND

PIN 16=V

* Both output will remain low as long as Set and Reset are

low, but the output states are unpredictable if Set and Reset

go high simultaneously

X = Don’t Care

Set

Reset

FUNCTION TABLE

Inputs

Clock

ORDERING INFORMATION

PIN ASSIGNMENT

TECHNICAL DATA

IN74HC112N Plastic

= -55° to 125° C for all

IN74HC112D SOIC

IN74HC112

packages

No Change

Outputs

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