lxt362 Intel Corporation, lxt362 Datasheet - Page 41

• Manufacturer Part Number: lxt362
• Description: Integrated T1 Lh/sh Transceiver For Ds1/dsx-1 Or Pri Applications
• Manufacturer: Intel Corporation

Datasheet
Transmit clock duty cycle
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
Receive clock duty cycle
Receive clock pulse width
Receive clock pulse width high
Receive clock pulse width low
RPOS/RNEG to RCLK rising time
RCLK rising to RPOS/RNEG hold time
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
3. Worst case conditions guaranteed by design only.
are for worst case jitter conditions.
Table 26. Master and Transmit Clock Timing Characteristics (See Figure 15)
Figure 15. Transmit Clock Timing
Table 27. Receive Timing Characteristics (See Figure 16)
Parameter
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362
2, 3
Parameter
2, 3
1,3
TCLKd
Sym
t
SUT
t
HT
Min
10
50
50
RLCKd
Sym
t
t
t
PWH
t
PWL
SUR
t
PW
HR
Typ
–
–
–
1
Min
260
40
Max
–
–
–
–
90
–
–
Typ
648
324
324
274
274
50
Unit
ns
ns
%
1
Max
388
60
–
–
–
–
Notes
Unit
ns
ns
ns
ns
ns
%
41